Improved process window using low-carbon Gexsil-x-yCyEpitaxial layers

1998 ◽  
Vol 535 ◽  
Author(s):  
A. Mocuta ◽  
D.W. Greve ◽  
R.M. Strong
Keyword(s):  
Strain Relaxation ◽  
Process Window ◽  
Epitaxial Layers ◽  
Low Carbon ◽  
Mos Capacitors ◽  
Beneficial Effects ◽  
Channel Thickness ◽  
Hole Confinement ◽  
Silicon Based ◽  
Boron Diffusivity

AbstractProcessing of silicon-based heterojunction devices is severely constrained by the relaxation of strained epitaxial layers. Generally the equilbrium critical thickness cannot be exceeded if high-temperature process steps such as oxidation and diffusion are performed. In this paper, we report on the beneficial effects of small amounts of carbon ( 0.2%) added to germanium-silicon epitaxial layers. We will show that such low concentrations result in a substantial decrease of boron diffusivity and strain relaxation. We will also report on the fabrication of GexSil-x-yCy heterostructure MOS capacitors with a channel thickness of 300 A° and a maximum germanium fraction of 50% A thermal oxidation at 800 ‘C was performed resulting in good C(VG) characteristics along with improved hole confinement.

scholarly journals Electrical Characterization of Postmetal Annealed Ultrathin TiN Gate Electrodes in Si MOS Capacitors

2016 ◽  
Vol 2016 ◽  
pp. 1-4 ◽  
Author(s):  
Z. N. Khan ◽  
S. Ahmed ◽  
M. Ali
Keyword(s):  
Electrical Characterization ◽  
Atomic Layer ◽  
Device Fabrication ◽  
Process Window ◽  
Gate Stacks ◽  
Mos Capacitors ◽  
Hafnium Silicate ◽  
Gate Electrodes ◽  
Layer Deposition ◽  
Tin Metal

Focusing on sub-10 nm Silicon CMOS device fabrication technology, we have incorporated ultrathin TiN metal gate electrode in Hafnium Silicate (HfSiO) based metal-oxide capacitors (MOSCAP) with carefully chosen Atomic Layer Deposition (ALD) process parameters. Gate element of the device has undergone a detailed postmetal annealed sequence ranging from 100°C to 1000°C. The applicability of ultrathin TiN on gate electrodes is established through current density versus voltage (J-V), resistance versus temperature (R-T), and permittivity versus temperature analysis. A higher process window starting from 600°C was intentionally chosen to understand the energy efficient behavior expected from ultrathin gate metallization and its unique physical state with shrinking thickness. The device characteristics in form of effective electronic mobility as a function of inverse charge density were also found better than those conventional gate stacks used for EOT scaling.

Stress Relaxation in Uniquely Oriented SiGe/Si Epitaxial Layers

1999 ◽  
Vol 594 ◽  
Author(s):  
M. E. Ware ◽  
R. J. Nemanich
Keyword(s):  
Stress Relaxation ◽  
Surface Morphology ◽  
Strain Relaxation ◽  
Epitaxial Layers ◽  
Misfit Dislocations ◽  
Strained Layers ◽  
Force Microscopy ◽  
Si Substrates ◽  
Atomic Force ◽  
Deposited Films

AbstractThis study explores stress relaxation of epitaxial SiGe layers grown on Si substrates with unique orientations. The crystallographic orientations of the Si substrates used were off-axis from the (001) plane towards the (111) plane by angles, θ = 0, 10, and 22 degrees. We have grown 100nm thick Si(1−x) Ge(x) epitaxial layers with x=0.3 on the Si substrates to examine the relaxation process. The as-deposited films are metastable to the formation of strain relaxing misfit dislocations, and thermal annealing is used to obtain highly relaxed films for comparison. Raman spectroscopy has been used to measure the strain relaxation, and atomic force microscopy has been used to explore the development of surface morphology. The Raman scattering indicated that the strain in the as-deposited films is dependent on the substrate orientation with strained layers grown on Si with 0 and 22 degree orientations while highly relaxed films were grown on the 10 degree substrate. The surface morphology also differed for the substrate orientations. The 10 degree surface is relatively smooth with hut shaped structures oriented at predicted angles relative to the step edges.

Strain relaxation of AlxGa1−xN epitaxial layers on GaN and SiC substrates

1999 ◽  
Vol 286 (1-2) ◽  
pp. 284-288 ◽  
Author(s):  
J Domagala ◽  
M Leszczynski ◽  
P Prystawko ◽  
T Suski ◽  
R Langer ◽  
...  
Keyword(s):  
Strain Relaxation ◽  
Epitaxial Layers

Strain relaxation in AlN epitaxial layers grown on GaN single crystals

1999 ◽  
Vol 205 (1-2) ◽  
pp. 31-35 ◽  
Author(s):  
R Langer ◽  
A Barski ◽  
A Barbier ◽  
G Renaud ◽  
M Leszczynski ◽  
...  
Keyword(s):  
Single Crystals ◽  
Strain Relaxation ◽  
Epitaxial Layers

Ultra-thin strain relaxed SiGe buffer layers with 40% Ge

2004 ◽  
Vol 809 ◽  
Author(s):  
Klara Lyutovich ◽  
Erich Kasper ◽  
Michael Oehme
Keyword(s):  
Surface Morphology ◽  
Point Defect ◽  
Strain Relaxation ◽  
Layer Growth ◽  
Buffer Layers ◽  
In Situ Monitoring ◽  
Process Window ◽  
Growth Stages ◽  
Growth Monitoring ◽  
Si Substrates

ABSTRACTVirtual substrates with ultra-thin SiGe strain relaxed buffers have been grown on Si substrates by a method employing point defect supersaturation in the growing layers. A concept of the point defect influence on the strain relaxation and on defect interactions in layers has been proposed. A method is developed to increase the degree of relaxation in sub-100 nm SiGe buffer layers and to provide a smooth surface morphology. Layer growth has been realized by solid source molecular beam epitaxy in a chamber equipped with an in situ monitoring system. One of the growth stages, performed at a very low temperature, serves the generation of point defects. Strain relaxation tunable up to the high degree and a crosshatch-free surface morphology are demonstrated in 40nm thick SiGe buffers which contain 40-45% Ge.Growth monitoring enables the control of the process window and the layer crystallization by a chosen mechanism.Virtual substrates produced by the described method were successfully tested in nMODFET structures.

Influences of Plasma Processed Interface Layers on Germanium MOS Devices with ALD Grown HfO2

2007 ◽  
Vol 996 ◽  
Author(s):  
Takuya Sugawara ◽  
Raghavasimhan Sreenivasan ◽  
Yasuhiro Oshima ◽  
Paul C. McIntyre
Keyword(s):  
Electrical Properties ◽  
Interface Layer ◽  
Hafnium Dioxide ◽  
Passivation Layer ◽  
Oxide Semiconductor ◽  
Flat Band ◽  
Mos Capacitors ◽  
Mos Devices ◽  
Interface Layers ◽  
Silicon Based

AbstractGermanium and hafnium-dioxide (HfO2) stack structures' physical and electrical properties were studied based on the comparison of germanium and silicon based metal-oxide-semiconductor (MOS) capacitors' electrical properties. In germanium MOS capacitor with oxide/oxynitride interface layer, larger negative flat-band-voltage (Vfb) shift compared with silicon based MOS capacitors was observed. Secondary ion mass spectrum (SIMS) characteristics of HfO2-germanium stack structure with germanium oxynitride (GeON) interfacial layer showed germanium out diffusion into HfO2. These results indicate that the germanium out diffusion into HfO2 would be the origin of the germanium originated negative Vfb shift. Using Ta3N5 layer as a germanium passivation layer, reduced Vfb shift and negligible hysteresis were observed. These results suggest that the selection of passivation layer strongly influences the electrical properties of germanium based MOS devices.

Passivation and Generation of States at P-Implanted Thermally Grown and Deposited N-Type 4H-SiC/SiO2 Interfaces

2016 ◽  
Vol 858 ◽  
pp. 697-700 ◽  
Author(s):  
Tomasz Sledziewski ◽  
Heiko B. Weber ◽  
Michael Krieger
Keyword(s):  
Electrical Properties ◽  
Response Time ◽  
Side Effect ◽  
Oxide Semiconductor ◽  
Epitaxial Layers ◽  
Interface Traps ◽  
Semiconductor Interface ◽  
Mos Capacitors ◽  
Thermally Grown Oxides ◽  
Thermally Grown

In this work the effect of phosphorus on the electrical properties of n-type 4H-SiC MOS capacitors is studied. Phosphorus ions are implanted into the epitaxial layers prior to the deposition of SiO2 by PECVD, in shallow depths and at concentrations at the oxide-semiconductor interface in the range of (5 x 1017…1 x 1019) cm-3. Those samples are compared with 31P-implanted 4H-SiC MOS capacitors with thermally grown oxides, which were primarily investigated in the previous work of the authors. It is shown that independently of the oxide technology phosphorus may lead to decrease of the density of interface traps, whose response time to the AC voltage is longer than 1 µs. The side-effect of the implantation of phosphorus is generation of the very fast interface states, which are able to follow the frequencies over 1 MHz.

scholarly journals Dislocation dynamics of strain relaxation in epitaxial layers

2001 ◽  
Vol 89 (11) ◽  
pp. 6069-6072 ◽  
Author(s):  
T. C. Wang ◽  
Y. W. Zhang ◽  
S. J. Chua
Keyword(s):  
Strain Relaxation ◽  
Dislocation Dynamics ◽  
Epitaxial Layers
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