Optimization of Microstructure and Dislocation Dynamics in InxGa1-xP Graded Buffers Grown on GaP by Movpe

1998 ◽  
Vol 535 ◽  
Author(s):  
A.Y. Kim ◽  
E.A. Fitzgerald
Keyword(s):  
Dislocation Dynamics ◽  
Limiting Factor ◽  
Threading Dislocation ◽  
High Quality ◽  
Design Rules ◽  
Dislocation Glide ◽  
Dislocation Densities ◽  
Threading Dislocation Density ◽  
Dislocation Pileups ◽  
Evolution Of Microstructure

AbstractTo engineer high-quality InxGal-xP graded buffers on GaP substrates (InxGa1-xP/GaP), we have explored the evolution of microstructure and dislocation dynamics in these materials. We show that the primarily limiting factor in obtaining high-quality InxGa1-xP/GaP is a new defect microstructure that we call branch defects. Branch defects pin dislocations and result in dislocation pileups that cause an escalation in threading dislocation density with continued grading. The morphology of branch defects is dominated by growth temperature, which can be used to suppress the strength or density of branch defects. In the absence of branch defects, we observe nearly ideal dislocation dynamics that are controlled by the kinetics of dislocation glide. This new understanding results in two primary design rules for achieving high-quality materials: 1) control branch defects, and 2) maximize dislocation glide kinetics. Combining these design rules into optimization strategies, we develop and demonstrate processes based on single and multiple growth temperatures. With optimization, threading dislocation densities below 5 × 106 cm−2 are achieved out to x = 0.39 and a nearly steady-state relaxation process is recovered.

Engineering Dislocation Dynamics in Inx(AlyGa1−y)1−xP Graded Buffers Grown on Gap by Movpe

1998 ◽  
Vol 510 ◽  
Author(s):  
A.Y. Kim ◽  
E.A. Fitzgerald
Keyword(s):  
Surface Roughness ◽  
Dislocation Density ◽  
Growth Conditions ◽  
Dislocation Nucleation ◽  
Dislocation Dynamics ◽  
Threading Dislocation ◽  
High Quality ◽  
Movpe Growth ◽  
Threading Dislocation Density ◽  
Buffer Design

AbstractTo engineer high-quality Inx(AlyGa1−y)1−x P/Ga1−xP graded buffers, we have explored the effects of graded buffer design and MOVPE growth conditions on material quality. We demonstrate that surface roughness causes threading dislocation density (TDD) to increase with continued grading: dislocations and roughness interact in a recursive, escalating cycle to form pileups that cause increasing roughness and dislocation nucleation. Experiments show that V/III ratio, temperature, and grading rate can be used to control dislocation dynamics and surface roughness in InxGa1−xP graded buffers. Control of these parameters individually has resulted in x = 0.34 graded buffers with TDD = 5 × 106 cm−2and roughness = 15 nm and a simple optimization has resulted in TDD = 3 × 106 cm −2and roughness = 10 un. Our most recent work has focused on more sophisticated optimization and the incorporation of aluminum for x > 0.20 to keep the graded buffer completely transparent above 545 nm. Given our results, we expect to achieve transparent, device-quality Inx(AlyGa1−y)1−x P/GaP graded buffers with TDD < 106 cm−2

Comparison of Buffer Layer Grading Approaches in InGaAs/GaAs (001)

2020 ◽  
Vol 29 (01n04) ◽  
pp. 2040002
Author(s):  
Johanna Raphael ◽  
Tedi Kujofsa ◽  
J. E. Ayers
Keyword(s):  
Lattice Mismatch ◽  
Strain Relaxation ◽  
Lower Surface ◽  
Dislocation Dynamics ◽  
Buffer Layers ◽  
Threading Dislocation ◽  
Dislocation Densities ◽  
Threading Dislocation Density ◽  
Dislocations Density ◽  
Graded Structures

Metamorphic semiconductor devices often utilize compositionally-graded buffer layers for the accommodation of the lattice mismatch with controlled threading dislocation density and residual strain. Linear or step-graded buffers have been used extensively in these applications, but there are indications that sublinear, superlinear, S-graded, or overshoot graded structures could offer advantages in the control of defect densities. In this work we compare linear, step-graded, and nonlinear grading approaches in terms of the resulting strain and dislocations density profiles using a state-of-the-art model for strain relaxation and dislocation dynamics. We find that sublinear grading results in lower surface dislocation densities than either linear or superlinear grading approaches.

Defect-Engineered Graded GexSi1-x Buffers on Si (001) with Extreme Low Threading Dislocation Density

1995 ◽  
Vol 378 ◽  
Author(s):  
G. Kissinger ◽  
T. Morgenstern ◽  
G. Morgenstern ◽  
H. B. Erzgräber ◽  
H. Richter
Keyword(s):  
Electron Microscopy ◽  
Transmission Electron Microscopy ◽  
Atomic Force Microscopy ◽  
Dislocation Density ◽  
Threading Dislocation ◽  
Force Microscopy ◽  
Atomic Force ◽  
Transmission Electron ◽  
Dislocation Densities ◽  
Threading Dislocation Density

AbstractStepwise equilibrated graded GexSii-x (x≤0.2) buffers with threading dislocation densities between 102 and 103 cm−2 on the whole area of 4 inch silicon wafers were grown and studied by transmission electron microscopy, defect etching, atomic force microscopy and photoluminescence spectroscopy.

Mid-10 cm−2 threading dislocation density in optimized high-Ge content relaxed graded SiGe on Si for III-V solar on Si

2004 ◽  
Vol 836 ◽  
Author(s):  
David M. Isaacson ◽  
Carl L. Dohrman ◽  
Arthur J. Pitera ◽  
Saurabh Gupta ◽  
Eugene A. Fitzgerald
Keyword(s):  
Solar Cells ◽  
Dislocation Density ◽  
Minority Carrier ◽  
Dislocation Nucleation ◽  
Threading Dislocation ◽  
High Quality ◽  
Significant Development ◽  
Threading Dislocation Density ◽  
Free Growth

ABSTRACTWe present a framework for obtaining high quality relaxed graded SiGe buffers on Si for III-V integration. By avoiding dislocation nucleation in Si1−xGex layers of x>0.96, we have achieved a relaxed Si0.04Ge0.96 platform on Si(001) offcut 2° that has a threading dislocation density of 7.4×105 cm−2. This 2° offcut orientation was determined to be the minimum necessary for APB-free growth of GaAs. Furthermore, we found that we could compositionally grade the Ge content in the high-Ge portion of the buffer at up to 17 %Ge μm−1 with no penalty to the dislocation density. The reduction in both threading dislocation density and buffer thickness exhibited by our method is an especially significant development for relatively thick minority-carrier devices which use III-V materials such as multi-junction solar cells.

Germanium Photodetectors for Silicon Microphotonics by Direct Epitaxy on Silicon

1999 ◽  
Vol 607 ◽  
Author(s):  
Hsin-Chiao Luan ◽  
Desmond R. Lim ◽  
Lorenzo Colace ◽  
Gianlorezo Masini ◽  
Gaetano Assanto ◽  
...  
Keyword(s):  
Chemical Vapor Deposition ◽  
Thermal Annealing ◽  
Vapor Deposition ◽  
Chemical Vapor ◽  
Annealing Process ◽  
Threading Dislocation ◽  
High Quality ◽  
Cyclic Annealing ◽  
Metal Semiconductor Metal ◽  
Dislocation Densities

AbstractWe have grown high-quality Ge epilayers on Si using two-step ultrahigh vacuum/chemical-vapor-deposition followed by post-growth cyclic thermal annealing. Cyclic annealing was effective in reducing threading dislocation densities. The annealing process was improved by optimizing the dislocation velocity. We fabricated and tested metal-semiconductor-metal planar photodetectors using Ge epilayers grown on Si. Our measurement showed an improvement in the photodetector performance as a result of the improved materials quality. The process described in this paper for making high-quality Ge on Si is uncomplicated and can be easily integrated with Si CMOS processes.

Mechanism for the Reduction of Threading Dislocation Densities in Si0.82Ge0.18 Films on Silicon on Insulator Substrates

2001 ◽  
Vol 673 ◽  
Author(s):  
E.M. Rehder ◽  
T.S. Kuan ◽  
T.F. Kuech
Keyword(s):  
Dislocation Density ◽  
Chemical Vapor ◽  
Dislocation Core ◽  
Extensive Study ◽  
Silicon On Insulator ◽  
Dislocation Dynamics ◽  
Threading Dislocation ◽  
Misfit Dislocations ◽  
Threading Dislocation Density ◽  
Soi Substrates

ABSTRACTWe have made an extensive study of Si0.82Ge0.18 film relaxation on silicon on insulator (SOI) substrates having a top Si layer 40, 70, 330nm, and 10[.proportional]m thick. SiGe films were deposited with a thickness up to 1.2[.proportional]m in an ultrahigh vacuum chemical vapor deposition system at 630°C. Following growth, films were characterized by X-ray diffraction and a dislocation revealing etch. The same level of relaxation is reached for each thickness of SiGe film independent of the substrate structure. Accompanying the film relaxation is the development of a tetragonal tensile strain in the thin Si layer of the SOI substrates. This strain reached 0.22% for the 1.2[.proportional]m film on the 40nm SOI and decreases with SOI thickness. The Si thickness of the SOI substrate also effected the threading dislocation density. For 85% relaxed films the density fell from 7×106 pits/cm2 on bulk Si to 103pits/cm2 for the 40, 70, and 330nm SOI substrates. The buried amorphous layer of the SOI substrate alters the dislocation dynamics by allowing dislocation core spreading or dislocation dissociation. The reduced strain field of these dislocations reduces dislocation interactions and the pinning that results. Without the dislocation pinning, the misfit dislocations can extend longer distances yielding a greatly reduced threading dislocation density.

X-Ray Topography Characterization of Large Diameter AlN Single Crystal Substrates

2020 ◽  
Vol 1004 ◽  
pp. 63-68
Author(s):  
Rafael Dalmau ◽  
Jeffrey Britt ◽  
Hao Yang Fang ◽  
Balaji Raghothamachar ◽  
Michael Dudley ◽  
...  
Keyword(s):  
Single Crystal ◽  
Large Diameter ◽  
Grazing Incidence ◽  
Threading Dislocation ◽  
Threading Dislocations ◽  
X Ray ◽  
Dislocation Densities ◽  
Transmission Geometry ◽  
Threading Dislocation Density

Large diameter aluminum nitride (AlN) substrates, up to 50 mm, were manufactured from single crystal boules grown by physical vapor transport (PVT). Synchrotron-based x-ray topography (XRT) was used to characterize the density, distribution, and type of dislocations. White beam topography images acquired in transmission geometry were used to analyze basal plane dislocations (BPDs) and low angle grain boundaries (LAGBs), while monochromatic beam, grazing incidence images were used to analyze threading dislocations. Boule diameter expansion, without the introduction of LAGBs around the periphery, was shown. A 48 mm substrate with a uniform threading dislocation density below 7.0 x 102 cm-2 and a BPD of 0 cm-2, the lowest dislocation densities reported to date for an AlN single crystal this size, was demonstrated.

TEM characterization of dislocation reduction processes in GaAs/Si

1989 ◽  
Vol 47 ◽  
pp. 590-591
Author(s):  
R.A. Herring ◽  
P.N. Uppal ◽  
S.P. Svensson ◽  
J.S. Ahearn
Keyword(s):  
Lattice Mismatch ◽  
Threading Dislocation ◽  
Threading Dislocations ◽  
Growth Interface ◽  
Dislocation Reduction ◽  
Dislocation Densities ◽  
Threading Dislocation Density ◽  
Interfacial Dislocations ◽  
Strained Layer Superlattices

A high density of interfacial dislocations are needed at the GaAs/Si interface to alleviate the 4% lattice mismatch between GaAs and Si. Some remnant dislocations thread through the epilayer and follow the growth interface. Current growth methods are not able to obtain acceptable threading dislocation densities (104 – 105) for devices. Many methods can be used to reduce the number of threading dislocations which include misorienting the substrate to enhance the slip of dislocations on specific [110]{111} planes, annealing during and after growth, and adding strained layer superlattices (SLS's) to block dislocations. Conventional TEM (CTEM), performed using a JEM 100c, has been used to characterize threading dislocations in the epilayer of a GaAs/Si material where in situ thermal annealing and SLS's force dislocation reactions and thereby reduce the threading dislocation density. Using TEM we have viewed dislocations under many two-beam diffraction conditions and with the help of a stereogram have determined their Burgers vectors (b), line directions (u) and habit planes (R).

High Quality Germanium Photodiodes on Silicon Substrates Using an Intermediate Chemical Mechanical Polishing Step

1997 ◽  
Vol 486 ◽  
Author(s):  
Srikanth B. Samavedam ◽  
Matthew T. Currie ◽  
Thomas A. Langdo ◽  
Steve M. Ting ◽  
Eugene A. Fitzgerald
Keyword(s):  
Dislocation Density ◽  
Chemical Mechanical Polishing ◽  
Mechanical Polishing ◽  
Quantum Yields ◽  
Threading Dislocation ◽  
Thermal Mismatch ◽  
High Quality ◽  
Si Substrates ◽  
Threading Dislocation Density ◽  
Graded Layers

AbstractGermanium (Ge) photodiodes are capable of high quantum yields and can operate at gigahertz frequencies in the 1–1.6 μm wavelength regime. The compatibility of SiGe alloys with Si substrates makes Ge a natural choice for photodetectors in Si-based optoelectronics applications. The large lattice mismatch (≈4%) between Si and Ge, however, leads to the formation of a high density of misfit and associated threading dislocations when uniform Ge layers are grown on Si substrates. High quality Ge layers were grown on relaxed graded SiGe/Si layers by ultra-high vacuum chemical vapor deposition (UHVCVD). Typically, as the Ge concentration in the graded layers increases, strain fields from underlying misfit dislocations result in increased surface roughness and the formation of dislocation pile-ups. The generation of pile-ups increases the threading dislocation density in the relaxed layers. In this study the pileup formation was minimized by growing on miscut (001) substrates employing a chemical mechanical polishing (CMP) step within the epitaxial structure. Other problems such as the thermal mismatch between Si and Ge, results in unwanted residual tensile stresses and surface microcracks when the substrates are cooled from the growth temperature. Compressive strain has been incorporated into the graded layers to overcome the thermal mismatch problem, resulting in crack-free relaxed cubic Ge on Si at room temperature. The overall result of the CMP step and the growth modifications have eliminated dislocation pile-ups, decreased gas-phase nucleation of particles, and eliminated the increase in threading dislocation density that occurs when grading to Ge concentrations greater than 70% Ge. The threading dislocation density in the Ge layers determined through plan view transmission electron microscopy (TEM) and etch pit density (EPD) was found to be in the range of 2 × 106/cm2. Ge p-n diodes were fabricated to assess the electronic quality and prove the feasibility of high quality photodetectors on Si substrates.

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