Engineering Dislocation Dynamics in Inx(AlyGa1−y)1−xP Graded Buffers Grown on Gap by Movpe

1998 ◽  
Vol 510 ◽  
Author(s):  
A.Y. Kim ◽  
E.A. Fitzgerald
Keyword(s):  
Surface Roughness ◽  
Dislocation Density ◽  
Growth Conditions ◽  
Dislocation Nucleation ◽  
Dislocation Dynamics ◽  
Threading Dislocation ◽  
High Quality ◽  
Movpe Growth ◽  
Threading Dislocation Density ◽  
Buffer Design

AbstractTo engineer high-quality Inx(AlyGa1−y)1−x P/Ga1−xP graded buffers, we have explored the effects of graded buffer design and MOVPE growth conditions on material quality. We demonstrate that surface roughness causes threading dislocation density (TDD) to increase with continued grading: dislocations and roughness interact in a recursive, escalating cycle to form pileups that cause increasing roughness and dislocation nucleation. Experiments show that V/III ratio, temperature, and grading rate can be used to control dislocation dynamics and surface roughness in InxGa1−xP graded buffers. Control of these parameters individually has resulted in x = 0.34 graded buffers with TDD = 5 × 106 cm−2and roughness = 15 nm and a simple optimization has resulted in TDD = 3 × 106 cm −2and roughness = 10 un. Our most recent work has focused on more sophisticated optimization and the incorporation of aluminum for x > 0.20 to keep the graded buffer completely transparent above 545 nm. Given our results, we expect to achieve transparent, device-quality Inx(AlyGa1−y)1−x P/GaP graded buffers with TDD < 106 cm−2

Mid-10 cm−2 threading dislocation density in optimized high-Ge content relaxed graded SiGe on Si for III-V solar on Si

2004 ◽  
Vol 836 ◽  
Author(s):  
David M. Isaacson ◽  
Carl L. Dohrman ◽  
Arthur J. Pitera ◽  
Saurabh Gupta ◽  
Eugene A. Fitzgerald
Keyword(s):  
Solar Cells ◽  
Dislocation Density ◽  
Minority Carrier ◽  
Dislocation Nucleation ◽  
Threading Dislocation ◽  
High Quality ◽  
Significant Development ◽  
Threading Dislocation Density ◽  
Free Growth

ABSTRACTWe present a framework for obtaining high quality relaxed graded SiGe buffers on Si for III-V integration. By avoiding dislocation nucleation in Si1−xGex layers of x>0.96, we have achieved a relaxed Si0.04Ge0.96 platform on Si(001) offcut 2° that has a threading dislocation density of 7.4×105 cm−2. This 2° offcut orientation was determined to be the minimum necessary for APB-free growth of GaAs. Furthermore, we found that we could compositionally grade the Ge content in the high-Ge portion of the buffer at up to 17 %Ge μm−1 with no penalty to the dislocation density. The reduction in both threading dislocation density and buffer thickness exhibited by our method is an especially significant development for relatively thick minority-carrier devices which use III-V materials such as multi-junction solar cells.

Mechanism for the Reduction of Threading Dislocation Densities in Si0.82Ge0.18 Films on Silicon on Insulator Substrates

2001 ◽  
Vol 673 ◽  
Author(s):  
E.M. Rehder ◽  
T.S. Kuan ◽  
T.F. Kuech
Keyword(s):  
Dislocation Density ◽  
Chemical Vapor ◽  
Dislocation Core ◽  
Extensive Study ◽  
Silicon On Insulator ◽  
Dislocation Dynamics ◽  
Threading Dislocation ◽  
Misfit Dislocations ◽  
Threading Dislocation Density ◽  
Soi Substrates

ABSTRACTWe have made an extensive study of Si0.82Ge0.18 film relaxation on silicon on insulator (SOI) substrates having a top Si layer 40, 70, 330nm, and 10[.proportional]m thick. SiGe films were deposited with a thickness up to 1.2[.proportional]m in an ultrahigh vacuum chemical vapor deposition system at 630°C. Following growth, films were characterized by X-ray diffraction and a dislocation revealing etch. The same level of relaxation is reached for each thickness of SiGe film independent of the substrate structure. Accompanying the film relaxation is the development of a tetragonal tensile strain in the thin Si layer of the SOI substrates. This strain reached 0.22% for the 1.2[.proportional]m film on the 40nm SOI and decreases with SOI thickness. The Si thickness of the SOI substrate also effected the threading dislocation density. For 85% relaxed films the density fell from 7×106 pits/cm2 on bulk Si to 103pits/cm2 for the 40, 70, and 330nm SOI substrates. The buried amorphous layer of the SOI substrate alters the dislocation dynamics by allowing dislocation core spreading or dislocation dissociation. The reduced strain field of these dislocations reduces dislocation interactions and the pinning that results. Without the dislocation pinning, the misfit dislocations can extend longer distances yielding a greatly reduced threading dislocation density.

High Quality Germanium Photodiodes on Silicon Substrates Using an Intermediate Chemical Mechanical Polishing Step

1997 ◽  
Vol 486 ◽  
Author(s):  
Srikanth B. Samavedam ◽  
Matthew T. Currie ◽  
Thomas A. Langdo ◽  
Steve M. Ting ◽  
Eugene A. Fitzgerald
Keyword(s):  
Dislocation Density ◽  
Chemical Mechanical Polishing ◽  
Mechanical Polishing ◽  
Quantum Yields ◽  
Threading Dislocation ◽  
Thermal Mismatch ◽  
High Quality ◽  
Si Substrates ◽  
Threading Dislocation Density ◽  
Graded Layers

AbstractGermanium (Ge) photodiodes are capable of high quantum yields and can operate at gigahertz frequencies in the 1–1.6 μm wavelength regime. The compatibility of SiGe alloys with Si substrates makes Ge a natural choice for photodetectors in Si-based optoelectronics applications. The large lattice mismatch (≈4%) between Si and Ge, however, leads to the formation of a high density of misfit and associated threading dislocations when uniform Ge layers are grown on Si substrates. High quality Ge layers were grown on relaxed graded SiGe/Si layers by ultra-high vacuum chemical vapor deposition (UHVCVD). Typically, as the Ge concentration in the graded layers increases, strain fields from underlying misfit dislocations result in increased surface roughness and the formation of dislocation pile-ups. The generation of pile-ups increases the threading dislocation density in the relaxed layers. In this study the pileup formation was minimized by growing on miscut (001) substrates employing a chemical mechanical polishing (CMP) step within the epitaxial structure. Other problems such as the thermal mismatch between Si and Ge, results in unwanted residual tensile stresses and surface microcracks when the substrates are cooled from the growth temperature. Compressive strain has been incorporated into the graded layers to overcome the thermal mismatch problem, resulting in crack-free relaxed cubic Ge on Si at room temperature. The overall result of the CMP step and the growth modifications have eliminated dislocation pile-ups, decreased gas-phase nucleation of particles, and eliminated the increase in threading dislocation density that occurs when grading to Ge concentrations greater than 70% Ge. The threading dislocation density in the Ge layers determined through plan view transmission electron microscopy (TEM) and etch pit density (EPD) was found to be in the range of 2 × 106/cm2. Ge p-n diodes were fabricated to assess the electronic quality and prove the feasibility of high quality photodetectors on Si substrates.

Low surface roughness and threading dislocation density Ge growth on Si (001)

2008 ◽  
Vol 310 (18) ◽  
pp. 4273-4279 ◽  
Author(s):  
Donghun Choi ◽  
Yangsi Ge ◽  
James S. Harris ◽  
Joel Cagnon ◽  
Susanne Stemmer
Keyword(s):  
Surface Roughness ◽  
Dislocation Density ◽  
Threading Dislocation ◽  
Threading Dislocation Density

Optical study of SiGe films grown with low temperature Si buffer

2001 ◽  
Vol 673 ◽  
Author(s):  
Y. H. Luo ◽  
J. Wan ◽  
J. L. Liu ◽  
K. L. Wang
Keyword(s):  
Raman Spectroscopy ◽  
Low Temperature ◽  
Molecular Beam ◽  
Growth Conditions ◽  
Buffer Layers ◽  
Threading Dislocation ◽  
Optical Study ◽  
High Quality ◽  
Atomic Force ◽  
Threading Dislocation Density

ABSTRACTIn this work, SiGe films on low temperature Si buffer layers were grown by solid-source molecular beam epitaxy and characterized by atomic force microscope, photoluminescence and Raman spectroscopy. Effects of the growth temperature and the thickness of the low temperature Si buffer were studied. It was demonstrated that using proper growth conditions of the low temperature Si buffer, the Si buffer became tensily strained and gave rise to the compliant effect. High-quality SiGe films with low threading dislocation density have been obtained.

High-Speed Growth of 4H-SiC Single Crystal Using Si-Cr Based Melt

2013 ◽  
Vol 740-742 ◽  
pp. 73-76 ◽  
Author(s):  
Motohisa Kado ◽  
Hironori Daikoku ◽  
Hidemitsu Sakamoto ◽  
Hiroshi Suzuki ◽  
Takeshi Bessho ◽  
...  
Keyword(s):  
Dislocation Density ◽  
Single Crystal ◽  
High Speed ◽  
High Rate ◽  
Threading Dislocation ◽  
High Quality ◽  
X Ray ◽  
Interface Kinetics ◽  
Threading Dislocation Density ◽  
Rate Limiting

In this study, we have investigated the rate-limiting process of 4H-SiC solution growth using Si-Cr based melt, and have tried high-speed growth. It is revealed that the rate-limiting process of SiC growth under our experimental condition is interface kinetics, which can be controlled by such factors as temperature and supersaturation of carbon. By enhancing the interface kinetics, SiC crystal has been grown at a high rate of 2 mm/h. The FWHM values of X-ray rocking curves and threading dislocation density of the grown crystals are almost the same as those of seed crystal. Possibility of high-speed and high-quality growth of 4H-SiC has been indicated.

Optimization of Microstructure and Dislocation Dynamics in InxGa1-xP Graded Buffers Grown on GaP by Movpe

1998 ◽  
Vol 535 ◽  
Author(s):  
A.Y. Kim ◽  
E.A. Fitzgerald
Keyword(s):  
Dislocation Dynamics ◽  
Limiting Factor ◽  
Threading Dislocation ◽  
High Quality ◽  
Design Rules ◽  
Dislocation Glide ◽  
Dislocation Densities ◽  
Threading Dislocation Density ◽  
Dislocation Pileups ◽  
Evolution Of Microstructure

AbstractTo engineer high-quality InxGal-xP graded buffers on GaP substrates (InxGa1-xP/GaP), we have explored the evolution of microstructure and dislocation dynamics in these materials. We show that the primarily limiting factor in obtaining high-quality InxGa1-xP/GaP is a new defect microstructure that we call branch defects. Branch defects pin dislocations and result in dislocation pileups that cause an escalation in threading dislocation density with continued grading. The morphology of branch defects is dominated by growth temperature, which can be used to suppress the strength or density of branch defects. In the absence of branch defects, we observe nearly ideal dislocation dynamics that are controlled by the kinetics of dislocation glide. This new understanding results in two primary design rules for achieving high-quality materials: 1) control branch defects, and 2) maximize dislocation glide kinetics. Combining these design rules into optimization strategies, we develop and demonstrate processes based on single and multiple growth temperatures. With optimization, threading dislocation densities below 5 × 106 cm−2 are achieved out to x = 0.39 and a nearly steady-state relaxation process is recovered.

High-Irradiance Degradation Studies of Metamorphic 1eV GaInAs Solar Cells

2012 ◽  
Vol 1432 ◽  
Author(s):  
Ryan M. France ◽  
Myles A. Steiner
Keyword(s):  
Solar Cells ◽  
Active Region ◽  
Dislocation Density ◽  
Dark Current ◽  
Degradation Mechanism ◽  
Control Cell ◽  
High Irradiance ◽  
Threading Dislocation ◽  
Threading Dislocation Density ◽  
Degradation Studies

ABSTRACTInitial tests are performed regarding the degradation of lattice-mismatched GaInAs solar cells. 1eV metamorphic GaInAs solar cells with 1-2×106 cm-2 threading dislocation density in the active region are irradiated with an 808 nm laser for 2 weeks time under a variety of temperature and illumination conditions. All devices show a small degradation in Voc that is logarithmic with time. The absolute loss in performance after 2 weeks illuminated at 1300 suns equivalent and 125°C is 7 mV Voc and 0.2% efficiency, showing these devices to be relatively stable. The dark current increases with time and is analyzed with a two-diode model. A GaAs control cell degrades at the same rate, suggesting that the observed degradation mechanism is not related to the additional dislocations in the GaInAs devices.

Sign in / Sign up

Export Citation Format

Share Document