Vertical Bipolar Transistors and a Merged 3–D Vertical Bipolar—Mos Device in Recrystallized Polysilicon

1985 ◽  
Vol 53 ◽  
Author(s):  
J.C. Sturm ◽  
J.F. Gibbons
Keyword(s):  
Minority Carrier ◽  
Strong Dependence ◽  
Three Dimensional ◽  
Bipolar Transistors ◽  
Bipolar Transistor ◽  
Current Gain ◽  
Collector Current ◽  
Beam Laser ◽  
P Type ◽  
Mos Device

ABSTRACTThe minority carrier properties of shaped—beam laser-recrystallized polysilicon films have been studied, leading to the successful fabrication of vertical bipolar transistors in these films and to the demonstration of a novel three—dimensional mergedvertical bipolar—MOS device. Experiments with lateral transistors established a minority carrier diffusion length of 4 μm in p—type recrystallized films. Vertical bipolar npn transistors with a base—width of 0.2 μm were fabricated in 0.75–μm—thick films using a polysilicon emitter technology. The strong dependence of the gain of the transistors on hydrogen annealing steps is described. With an Ar:H plasma anneal to decrease base—emitter space—charge region recombination, a common—emitter current gain of 100 was possible. The bipolar transistor technology was then used to develop a 3—D fourterminal merged verticalbipolar—MOS device in a recrystallized film. It consists of the three terminals of a bipolar transistor plus a fourth underlying terminal which serves to switch the collector current on or off. A simple model for the device is presented.

Current Gain of 4H-SiC Bipolar Transistors Including the Effect of Interface States

2005 ◽  
Vol 483-485 ◽  
pp. 889-892 ◽  
Author(s):  
Martin Domeij ◽  
Erik Danielsson ◽  
Hyung Seok Lee ◽  
Carl Mikael Zetterling ◽  
Mikael Östling
Keyword(s):  
Side Wall ◽  
Interface States ◽  
Bipolar Transistors ◽  
Current Gain ◽  
Poor Agreement ◽  
Collector Current ◽  
Bandgap Narrowing ◽  
Pulsed Measurements ◽  
Emitter Junction ◽  
Constant Distribution

The current gain (b) of 4H-SiC BJTs as function of collector current (IC) has been investigated by DC and pulsed measurements and by device simulations. A measured monotonic increase of b with IC agrees well with simulations using a constant distribution of interface states at the 4H-SiC/SiO2 interface along the etched side-wall of the base-emitter junction. Simulations using only bulk recombination, on the other hand, are in poor agreement with the measurements. The interface states degrade the simulated current gain by combined effects of localized recombination and trapped charge that influence the surface potential. Additionally, bandgap narrowing has a significant impact by reducing the peak current gain by about 50 % in simulations.

Current Gain of an AlGaN/GaN Heterojunction Bipolar Transistor

2001 ◽  
Vol 680 ◽  
Author(s):  
Yumin Zhang ◽  
P. Paul Ruden
Keyword(s):  
Electron Transport ◽  
Hybrid Model ◽  
Carrier Transport ◽  
Effective Field ◽  
Structure Design ◽  
Bipolar Transistor ◽  
Heterojunction Bipolar Transistor ◽  
Current Gain ◽  
Design Parameters ◽  
Collector Current

ABSTRACTA novel hybrid model and simulation results for an advanced, graded base AlGaN/GaN heterojunction bipolar transistor structure are presented. The base of the n-p-n HBT examined has two parts, a linearly graded AlGaN layer on the emitter side and a heavily p-doped GaN layer on the collector side. In the hybrid model developed here the potential profile is first calculated self-consistently in the biased state taking into account ionized impurity charges, polarization charges, and majority carrier charges. The minority carrier transport is examined subsequently. Injection of electrons from the emitter is modeled as a thermionic emission process. The minority electron transport process in the graded region is drift-dominated due to the large built-in effective field strength. In the low-field GaN layer of the base, electron transport is assumed to be diffusion-dominated. High-level injection effects are modeled in the framework of the Gummel-Poon model. Example structure design parameters are presented and it is found that the calculated current gain can be greater than 25, with a collector current density of 104A/cm2.

Hot Carrier Degradation of Gain in Bipolar Transistors

1995 ◽  
Vol 391 ◽  
Author(s):  
Isik C. Kizilyalli ◽  
Jeff D. Bude
Keyword(s):  
Impact Ionization ◽  
High Energy ◽  
Bipolar Transistors ◽  
Bipolar Transistor ◽  
Current Gain ◽  
Exponential Dependence ◽  
Hot Electron ◽  
Hot Carrier ◽  
Bicmos Technology ◽  
Doping Profiles

AbstractIn this paper hot carrier related aging of n-p-n bipolar transistors is investigated experimentally and theoretically to bring physical insight into the bipolar transistor hFE (common emitter current gain) degradation. Electrical stress experiments are performed on transistors with different base doping profiles at varying temperatures. Detailed process simulations are performed to determine the doping profiles of the base-emitter junction. Monte Carlo transport simulations are then performed at different temperatures and bias conditions to determine the electron and hole distribution functions in the baseemitter junction. AT&T's 0.8 μ.m BICMOS technology is used to fabricate the experimental bipolar transistor structures. For this non-self aligned technology we attribute hFE degradation to the presence of hot holes and secondary electrons which are generated by hot hole impact ionization. This feed-back due to impact ionization has a dominant effect on the high energy tails of the distribution of both holes and electrons even when the overall current multiplication is low. Simple hot electron energy transport models do not contain the complexity to properly describe ionization feedback and carrier heating, and are therefore inadequate. An exponential dependence of the transistor lifetime on BVEBO is deduced for constant voltage stress (Vstress < BVEBO) conditions, confirming the importance of secondaries in the process of degradation.

scholarly journals Investigation of the static current gain for InP/InGaAs single heterojunction bipolar transistor

2019 ◽  
Vol 13 (3) ◽  
pp. 1345
Author(s):  
Jihane Ouchrif ◽  
Abdennaceur Baghdad ◽  
Aicha Sshel ◽  
Abdelmajid Badri ◽  
Abdelhakim Ballouk
Keyword(s):  
Heterojunction Bipolar Transistors ◽  
Communication Systems ◽  
Bipolar Transistors ◽  
Bipolar Transistor ◽  
Heterojunction Bipolar Transistor ◽  
Current Gain ◽  
Technological Parameters ◽  
Device Structure ◽  
Optimal Values ◽  
Output Characteristics

<p>Heterojunction Bipolar Transistors are being used increasingly in communication systems due to their electrical performances. They are considered as excellent electronic devices. This paper presents an investigation of the static current gain β based on two technological parameters related to the device geometry for InP/InGaAs Single Heterojunction Bipolar Transistor (SHBT). These parameters are the base width  and the emitter length . We used Silvaco’s TCAD tools to design the device structure, and to extract the static current gain β from I-V output characteristics figures. According to this investigation, we determined the optimal values of the examined parameters which allow obtaining the highest static current gain β.</p>

Device Simulation and Design Optimization for Diamond Based Insulated-gate Bipolar Transistors

2006 ◽  
Vol 956 ◽  
Author(s):  
Haitao Ye ◽  
Niall Tumilty ◽  
David Garner ◽  
Richard B. Jackman
Keyword(s):  
Carrier Concentration ◽  
Potential Distribution ◽  
Device Simulation ◽  
Bipolar Transistors ◽  
Bipolar Transistor ◽  
Current Gain ◽  
Two Dimensional ◽  
Insulated Gate Bipolar Transistors ◽  
Base Region ◽  
Insulated Gate Bipolar Transistor

ABSTRACTA diamond based insulated gate bipolar transistor is incorporated into a two-dimensional device simulator (MEDICI) to examine the current gain (β) and potential distribution across the device. Initially, work has focused on an important component of IGBT structure, the PNP bipolar transistor, which has been simulated and is reported upon in this paper. Empirical parameters for emitter and collector regions were used. Various carrier concentrations for base region were used to optimize the simulation. It was found that decreasing the thickness of base region leads to an increase in current gain. A buffer layer is needed to prevent the punch-through at low carrier concentration in the base region. Various approaches of increasing the current gain are also discussed in this paper.

The Role of the Si-SiO2 (CVD) Interface in Degradation Effects for High-Speed Bipolar Transistors

1995 ◽  
Vol 378 ◽  
Author(s):  
J.-Q. Lü ◽  
S. Schöttl ◽  
E. Stefanov ◽  
F. Koch ◽  
R. Mahnkopf ◽  
...  
Keyword(s):  
High Speed ◽  
Tunneling Current ◽  
Bipolar Transistors ◽  
Bipolar Transistor ◽  
Current Gain ◽  
Current Increase ◽  
Base Current ◽  
2D Simulation ◽  
Trap Assisted Tunneling ◽  
Emitter Junction

AbstractThe intent of the present work is to analyze device degradation and reliability in terms of their microscopic origins. The base-emitter junction of the advanced, “double-poly”, self-aligned bipolar transistor contacts the SiO2 sidewall spacer. During normal circuit operation, the base-emitter junction experiences a reverse bias which as a stress in time degrades the current gain of the transistor. Both a decrease of the gain, as well as an increase in the noise are observed. The forward base current increase as a function of stress time follows △IB ∼ tn. We present evidence that the defects are occurring at the Si-Si02 interface from perimeter to area comparisons. The weak temperature dependence of the forward base current in degraded transistors shows that trap-assisted tunneling current through the Si-SiO2 interface states is involved. The random-telegraph-signals observed for the first time in a silicon bipolar transistor are a direct identification of damage at the Si-SiO2 interface. 2D simulation of the potential and field near the interface allows us to show that damage can be expected.

Reduction of Base Access Resistance in AlGaN/GaN Heterojunction Bipolar Transistors using GaInN Base Cap Layer and Selective Epitaxial Growth

2005 ◽  
Vol 892 ◽  
Author(s):  
Jay M Shah ◽  
Thomas Gessmann ◽  
Hong Luo ◽  
Yangang Xi ◽  
Kaixuan Chen ◽  
...  
Keyword(s):  
Contact Resistance ◽  
Epitaxial Growth ◽  
Heterojunction Bipolar Transistors ◽  
Bipolar Transistors ◽  
Current Gain ◽  
Selective Epitaxial Growth ◽  
Offset Voltage ◽  
Specific Contact ◽  
Access Resistance ◽  
P Type

AbstractOne of the major challenges affecting the performance of Npn AlGaN/GaN heterojunction bipolar transistors (HBTs) is the high base access resistance, which is comprised of the base contact resistance and the base bulk resistance. A novel concept is proposed to reduce the base access resistance in Npn AlGaN/GaN HBTs by employing polarization-enhanced contacts and selective epitaxial growth of the base and emitter. In addition, this technique reduces the exposed base surface area, which results in a lower surface recombination current. Such a structure would enable better performance of AlGaN/GaN HBTs in terms of higher current gain and a lower offset voltage. Theoretical calculations on polarization-enhanced contacts predict p-type specific contact resistance lower than 10-5 Ωcm2. Experimental results using transmission line measurement (TLM) technique yield specific contact resistances of 5.6×10-4 Ωcm2 for polarization-enhanced p-type contacts and 7.8×10-2 Ωcm2 for conventional p-type contacts.

scholarly journals Effects of Temperature and Stress on the InGaP/GaAs Heterojunction Phototransistor

2021 ◽  
Vol 19 (6.2) ◽  
pp. 28
Author(s):  
Phuc Hong Than ◽  
Tran Thi Tra Vinh ◽  
Le Thi My Hanh ◽  
Than Quang Tho ◽  
Nguyen Vu Anh Quang ◽  
...  
Keyword(s):  
Heterojunction Bipolar Transistors ◽  
Stress Test ◽  
Optical Gain ◽  
Bipolar Transistors ◽  
Current Gain ◽  
Temperature Dependent ◽  
Collector Current ◽  
Electrical Stress ◽  
Before And After ◽  
Higher Temperature

Although the effects of electrical stress and temperature on the performance of the InGaP/GaAs heterojunction bipolar transistors (HBTs) have been widely studied and reported, little or none was reported for the InGaP/GaAs heterojunction phototransistors (HPTs) in the literature. In this paper, we discuss the temperature-dependent characteristic of InGaP/GaAs HPTs before and after electrical stress and assess the effectiveness of the emitter-ledge passivation, which was found to effectively keep the InGaP/GaAs HBTs from degrading at higher temperature or after an electrical stress. The emitter-ledge passivation is also effective keeping a higher optical gain even at higher temperature. An electrical stress was given to the HPTs by keeping the collector current at 60 mA for 15 min. Since the collector current density as an electrical stress is 24 A/cm2 and much smaller than the stress usually given to smaller HBTs for the stress test, the decreased optical gain was not observed when it was given at room temperature. However, when it was given at 420 K, significant decreases of the current gain and optical gain were observed at any temperature. Nevertheless, the emitter-ledge passivation was found effective in minimizing the decreases of the current gain and optical gain.

Noninjecting, high-barrier junctions on p-type silicon

1985 ◽  
Vol 63 (6) ◽  
pp. 723-726
Author(s):  
N. Garry Tarr
Keyword(s):  
Minority Carrier ◽  
Bipolar Transistors ◽  
Carrier Injection ◽  
Type Silicon ◽  
Current Densities ◽  
Heavily Doped ◽  
P Type ◽  
Ultrathin Oxide ◽  
Transient Measurements

The fabrication of junctions with very low minority-carrier injection ratios and reasonably good diode characteristics on p-type silicon is reported. These junctions were formed by growing an ultrathin oxide layer on a monocrystalline substrate, depositing polysilicon heavily doped in situ with phosphorus over the oxide, overlaying the polysilicon with aluminum, and then annealing the resulting sandwich structure at temperatures in the range 400–450 °C. The junctions can exhibit leakage current densities below 10−6 A∙cm−2 at moderate reverse bias and reverse breakdown voltages in excess of 20 V. The absence of minority-carrier injection has been demonstrated by diode reverse recovery transient measurements and by the fabrication of bipolar transistors employing these junctions as emitters.

GaAs Heterojunction Bipolar Transistor Device and IC Technology

1988 ◽  
Vol 144 ◽  
Author(s):  
Michael E. Kim ◽  
Aaron K. Oki ◽  
James B. Camou ◽  
Gary M. Gorman ◽  
Donald K. Umemoto ◽  
...  
Keyword(s):  
Integrated Circuit ◽  
Field Effect Transistors ◽  
Harmonic Distortion ◽  
Bipolar Transistor ◽  
Heterojunction Bipolar Transistor ◽  
Current Gain ◽  
Noise Power ◽  
Single Chip ◽  
Collector Current ◽  
Rf Performance

ABSTRACTGaAs/AlGaAs N-p-n heterojunction bipolar transistor (GaAs HBT) device and integrated circuit technology which offers key advantages over advanced silicon bipolar and III-V compound field-effect transistors is maturing towards system insertion. The TRW device and IC fabrication process, basic HBT dc and RF performance, examples of device and IC applications, and technology qualification work are presented and serves as a basis for discussing overall technology issues and impact. A relaxed 3-μm emitter-up, self-aligned base ohmic metal (SABM) HBT process and simplified molecularbeam epitaxial profiles are used for near-term producibility. The HBTs have simultaneous fT, fmax≈20–40 GHz and dc current gain ß≈50–100 at collector current density JC=3 kA/cm2 and Early voltage VA≈200–300 with capability for MSI-LSI integration levels. Versatile dc-20 GHz analog, 3–6 Gb/s digital, and 2–3 Gs/s A/D conversion functions are demonstrated with a common 3-μm SABM HBT process which facilitates single-chip multifunctional capability. Key improvements are realized over Si bipolar and GaAs-related FET (e.g. MESFET and HEMT) approaches in operational frequency, gain-bandwidth product, harmonic distortion, 1/f noise, power consumption, and size reduction.

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