Optimization of Ti and Co Self-Aligned Silicide RTP for 0.10 μm CMOS

1998 ◽  
Vol 514 ◽  
Author(s):  
J. A. Kittl ◽  
Q. Z. Hong ◽  
H. Yang ◽  
N. Yu ◽  
M. Rodder ◽  
...  
Keyword(s):  
Contact Resistance ◽  
Sheet Resistance ◽  
Cmos Technology ◽  
Successful Implementation ◽  
Optimal Process ◽  
Shallow Junction ◽  
Low Resistance ◽  
Mo Doping ◽  
One Step

ABSTRACTAs CMOS technologies are scaled to 0.10 μm and beyond, self-aligned silicide (salicide) processes find difficult challenges. As junction depths and linewidths are scaled, achieving both low sheet resistance and low contact resistance maintaining low diode leakage becomes increasingly difficult. In this paper we present studies of Ti and Co salicide processes implemented into a 0.10 μm CMOS technology. We show that both for Ti and Co, the optimization of RTP parameters plays a crucial roll in achieving a successful implementation. For Co salicide, optimization of RTP conditions results in elimination of shallow junction leakage (its main scaling problem). Two-step RTP and one-step RTP Ti salicide processes are compared, showing the advantages of one-step RTP. The RTP process windows for low resistance narrow gates (the main scaling issue for Ti salicide) are analyzed. Processes with pre-amorphization, with Mo doping and with a combination of both are compared. An optimal process using Mo and preamorphization implants and one-step RTP is shown to result in excellent device characteristics and low resistance to 0.06 μm gates.

Optimization of Ti and Co Self-Aligned Silicide RTP for 0.10 μm Cmos

1998 ◽  
Vol 525 ◽  
Author(s):  
J. A. Kittl ◽  
Q. Z. Hong ◽  
H. Yang ◽  
N. Yu ◽  
M. Rodder ◽  
...  
Keyword(s):  
Contact Resistance ◽  
Sheet Resistance ◽  
Cmos Technology ◽  
Successful Implementation ◽  
Optimal Process ◽  
Shallow Junction ◽  
Low Resistance ◽  
Mo Doping ◽  
One Step

ABSTRACTAs CMOS technologies are scaled to 0.10 μm and beyond, self-aligned silicide (salicide) processes find difficult challenges. As junction depths and linewidths are scaled, achieving both low sheet resistance and low contact resistance maintaining low diode leakage becomes increasingly difficult. In this paper we present studies of Ti and Co salicide processes implemented into a 0.10 μm CMOS technology. We show that both for Ti and Co, the optimization of RTP parameters plays a crucial roll in achieving a successful implementation. For Co salicide, optimization of RTP conditions results in elimination of shallow junction leakage (its main scaling problem). Two-step RTP and one-step RTP Ti salicide processes are compared, showing the advantages of one-step RTP. The RTP process windows for low resistance narrow gates (the main scaling issue for Ti salicide) are analyzed. Processes with pre-amorphization, with Mo doping and with a combination of both are compared. An optimal process using Mo and preamorphization implants and one-step RTP is shown to result in excellent device characteristics and low resistance to 0.06 μm gates.

Low Temperature Formation of C54 TiSi2 Bypassing the C49 Phase: Effect of Si Crystallinity, Metallic Impurities and Applications TO 0.10 μm CMOS

1998 ◽  
Vol 514 ◽  
Author(s):  
J. A. Kittl ◽  
M. A Gribelyuk ◽  
S. B. Samavedam ◽  
Q. Z. Hong ◽  
N. Yu ◽  
...  
Keyword(s):  
Sheet Resistance ◽  
Cmos Technology ◽  
High Resistivity ◽  
Si Substrates ◽  
Early Stages ◽  
Mo Doping ◽  
Large Structures ◽  
Diffusion Limited ◽  
Transmission Electron ◽  
Phase Sequence

ABSTRACTThe mechanism and evolution from the early stages of the Ti/Si reaction by rapid thermal processing (RTP) at 650°C in the presence of Mo doping was studied and compared to the case without Mo doping; for amorphous, polycrystalline and single crystal (100) Si substrates. It was found that for Mo doped polycrystalline Si or Mo doped amorphous Si, the low resitivity C54 TiSi2 phase nucleates at the Ti/Si interface and grows following diffusion limited kinetics, bypassing the nucleation of the high resistivity C49 TiSi2 phase. The conventional phase sequence, with C49 TiSi 2 nucleation and growth, was observed on Mo doped (100) Si and all samples without Mo. The mechanism of early C54 nucleation was identified by high resolution transmission electron microscopy (HRTEM): at early stages of the reaction, precursor silicide phases lattice matched to C54 TiSi2 nucleate at the Ti/Mo doped Si interface, and act as templates for epitaxial nucleation of C54 TiSi2. Two such phases were observed, MoSi2 and a phase with spacings of 2.26 Å and 4.2 Å. Image simulations suggest that the structure of the second template phase is based on Mo5Si3. Similar kinetics were observed on large structures and narrow lines for Mo doped Si (except for the case of (100) Si), indicating that this growth mechanism eliminates the linewidth dependence. Implementation on a 0.10 μm CMOS technology of a process combining Mo doping with pre-amorphization (PAI) achieves low source/drain (S/D) sheet resistance, and the first Ti salicide process with low gate sheet resistance down to 0.06 μm.

scholarly journals Application Examples for the Different Measurement Modes of Electrical Properties of the Solar Cells

2014 ◽  
Vol 59 (1) ◽  
pp. 247-252 ◽  
Author(s):  
M. Musztyfaga-Staszuk ◽  
L.A. Dobrzanski ◽  
S. Rusz ◽  
M. Staszuk
Keyword(s):  
Solar Cells ◽  
Electrical Properties ◽  
Contact Resistance ◽  
Sheet Resistance ◽  
Cross Sections ◽  
Standard Technique ◽  
Photovoltaic Cell ◽  
Metal Resistance ◽  
Silicon Wafers ◽  
Formation Technique

Abstract The aim of the paper was to apply the newly developed instruments ‘Corescan’ and ‘Sherescan’ in order to measure the essential parameters of producing solar cells in comparison with the standard techniques. The standard technique named the Transmission Line Method (TLM) is one way to monitor contacting process to measure contact resistance locally between the substrate and metallization. Nowadays, contact resistance is measured over the whole photovoltaic cell using Corescanner instrument. The Sherescan device in comparison with standard devices gives a possibility to measure the sheet resistance of the emitter of silicon wafers and determine of both P/N recognition and metal resistance. The Screen Printing (SP) method is the most widely used contact formation technique for commercial silicon solar cells. The contact resistance of manufactured front metallization depends of both the paste composition and co-firing conditions. Screen printed front side metallization and next to co-fired in the infrared conveyor furnace was carried out at various temperature from 770°C to 920°C. The silver paste used in the present paper is commercial. The investigations were carried out on monocrystalline silicon wafers. The topography of co-fired in the infrared belt furnace front metallization was investigated using the atomic force microscope and scanning electron microscope (SEM). There were researched also cross sections of front contacts using SEM microscope. Front contacts of the solar cells were formed on non-textured silicon surface with coated antireflection layer. On one hand, based on electrical properties investigations using Sherescan instrument it was obtained the knowledge of the emitter sheet resistance across the surface of a wafer, what is essential in optimizing the emitter diffusion process. On the other hand, it was found using Corescan instrument that the higher temperature apparently results in a strongly decreased contact resistance.

scholarly journals Solution-Grown Zn/Al Layered Double Hydroxide Nanoplatelets onto Al Thin Films: Fine Control of Position and Lateral Thickness

2015 ◽  
Vol 2015 ◽  
pp. 1-8 ◽  
Author(s):  
D. Scarpellini ◽  
C. Leonardi ◽  
A. Mattoccia ◽  
L. Di Giamberardino ◽  
P. G. Medaglia ◽  
...  
Keyword(s):  
Layered Double Hydroxide ◽  
Cmos Technology ◽  
Aluminum Film ◽  
Aluminum Layer ◽  
Final Thickness ◽  
Wet Chemistry ◽  
Residual Aluminum ◽  
Fine Control ◽  
One Step ◽  
Double Hydroxide

We have grown nanostructured films of Zn/Al Layered Double Hydroxide (LDH) on different substrates by combining the deposition of an aluminum micropatterned thin layer with a successive one-step room-temperature wet-chemistry process. The resulting LDH film is made of lamellar-like nanoplatelets mainly oriented perpendicular to the substrate. Since the aluminum layer acts as both reactant and seed for the synthesis of the LDH, the growth can be easily confined with submicrometric-level resolution (about ±0.5 μm) by prepatterning the aluminum layer with conventional photolithographic techniques. Moreover, we demonstrate real-time monitoring of the LDH growth process by simply measuring the resistance of the residual aluminum film. If the aluminum layer is thinner than 250 nm, the morphology of LDH nanoplatelets is less regular and their final thickness linearly depends on the initial amount of aluminum. This peculiarity allows accurately controlling the LDH nanoplatelet thickness (with uncertainty of about ±10%) by varying the thickness of the predeposited aluminum film. Since the proposed growth procedure is fully compatible with MEMS/CMOS technology, our results may be useful for the fabrication of micro-/nanodevices.

Effects of Carbon Co-Implantation on Transient Enhanced Diffusion and Performances of the Phosphorus Doped Ultra-Shallow Junction Nano NMOSFET

2013 ◽  
Vol 284-287 ◽  
pp. 98-102
Author(s):  
Hung Yu Chiu ◽  
Yean Kuen Fang ◽  
Feng Renn Juang
Keyword(s):  
Cmos Technology ◽  
Shallow Junction ◽  
Enhanced Diffusion ◽  
Transient Enhanced Diffusion ◽  
Technology Applications ◽  
Implantation Process ◽  
Phosphorus Doped

The carbon (C) co-implantation and advanced flash anneal were employed to form the ultra shallow junction (USJ) for future nano CMOS technology applications. The effects of the C co-implantation process on dopant transient enhanced diffusion (TED) of the phosphorus (P) doped nano USJ NMOSFETs were investigated in details. The USJ NMOSFETs were prepared by a foundry’s 55 nano CMOS technology. Various implantation energies and doses for both C and P ions were employed. Results show the suppression of the TED is strongly dependent on both C and P implantation conditions. Besides, the mechanisms of P TED and suppression by C ion co-implantation were illustrated comprehensively with schematic models.

One-Step Fabrication and Functionalization of Nanostructured Silicon Surfaces for Advanced Sensing Applications

2020 ◽  
Vol 312 ◽  
pp. 154-159
Author(s):  
Alexander Yuryevich Mironenko ◽  
Mikhail Tutov ◽  
Alexander Konstantinovich Chepak ◽  
Eugeny Mitsai ◽  
Alexander A. Sergeev ◽  
...  
Keyword(s):  
Laser Processing ◽  
Laser Energy ◽  
High Spatial Frequency ◽  
Laser Pulses ◽  
Successful Implementation ◽  
Experimental Conditions ◽  
Sensing Applications ◽  
Direct Laser ◽  
Fs Laser ◽  
One Step

Direct laser processing of various materials with nano- and femtosecond (fs) laser pulses is known to be a facile and inexpensive technology for fabrication of various surface morphologies. Since ultrafast deposition of the laser energy to target material typically creates unique experimental conditions with extremely high pressure and temperature, we hypothesized that carrying out this process in anhydrous non-oxidizing environment containing functionalizing agent (fluorophore with vinyl functional group) will allow one-step fabrication and subsequent functionalization of the surface of high-n material. In this paper, we demonstrate successful implementation of this idea by fabricating high-spatial-frequency laser-induced periodic surface structures (LIPSS) via direct fs-pulse ablation of bulk crystalline Si wafer immersed in solution of N-vinylcarbazole in toluene. Laser processing with linearly polarized fs-laser pulses was found to produce LIPSS with a characteristic period around 100 nm functionalized with N-vinylcarbazole molecules via photo-activated hydrosililation reaction. The unique LIPSS with hierarchical roughness and remarkable light trapping performance functionalized with sensory fluorophore show high sensitivity due to implementation of surface enhanced fluorescence effect. By using N-vinylcarbazole as functionalizing agent we demonstrate one-step fabrication of high-performance sensor for detecting nitrobenzene in water with a detection limit of 40 nM.

Stable Low Resistance Ohmic Contacts To p-GaN

2001 ◽  
Vol 680 ◽  
Author(s):  
Mi-Ran Park ◽  
Wayne A. Anderson
Keyword(s):  
Contact Resistance ◽  
Photoelectron Spectroscopy ◽  
Ohmic Contacts ◽  
Depth Profiling ◽  
Force Microscopy ◽  
Low Resistance ◽  
Atomic Force ◽  
Current Voltage ◽  
Thermionic Field Emission ◽  
P Type

ABSTRACTStable and low-resistance Ohmic contacts are especially important for laser diodes where high current levels are required. Good contacts are especially difficult on p-type GaN which was the motivation for this study. The GaN was epitaxially grown on (0001) sapphire substrates by MOCVD. Resistivity of this layer was 3.5 Ohm-cm and thickness was 2 microns. After conventional cleaning followed by treatment in boiling HNO3: HCl (1:3), metallization was by thermally evaporating 40 nm Au / 60 nm Ni or 70 nm Au / 55 nm Pd. Heat treatment in O2 + N2 at various temperatures followed, with best results at 600 °C or 700 °C, respectively. Best values of the contact resistance were 1.8×10−4 Ohm-cm2 for Pd/Au and 2.65×10−4 Ohm-cm2 for Ni/Au contacts. After repetitive cycling from room temperature to 600 °C, the Ni contacts were very stable and more stable than the Pd contacts. X-ray photoelectron spectroscopy depth profiling showed the Ni contacts to be NiO followed by Au at the interface for the Ni/Au contacts whereas the Pd/Au contacts exhibited a Pd: Au solid solution. Some contacts were quenched in liquid nitrogen following sintering. These contacts were much more uniform under atomic force microscopy examination and gave a 3 times lower contact resistance with the Ni/Au design. Current-voltage-temperature analysis revealed that conduction was predominantly by thermionic field emission.

Influence of amorphization depth on sheet resistance in shallow junction formation with B cluster implantation

2009 ◽  
Author(s):  
Yoji Kawasaki ◽  
Yoshiki Maruyama ◽  
Hidefumi Yoshimura ◽  
Hiroshi Miyatake ◽  
Kentaro Shibahara
Keyword(s):  
Sheet Resistance ◽  
Shallow Junction ◽  
Junction Formation

The Role of Ni in the Formation of Low Resistance Ni–Ge–Au Ohmic Contacts to n+ GaAs Heterostructures

1999 ◽  
Vol 14 (4) ◽  
pp. 1261-1271 ◽  
Author(s):  
Nancy E. Lumpkin ◽  
Gregory R. Lumpkin ◽  
Mark G. Blackford
Keyword(s):  
Contact Resistance ◽  
Ohmic Contacts ◽  
Wetting Agent ◽  
Dopant Distribution ◽  
Low Resistance ◽  
Ni Content ◽  
Alloy Microstructure

Nickel is a commonly used wetting agent in alloyed Au–Ge ohmic contacts to n-GaAs, resulting in uniformity improvements to the morphology and contact resistance. In order to study the role of Ni in Ni–Ge–Au alloys, we have fabricated samples with varying Ni content and characterized them using electron microbeam techniques. Our data indicate the amount of Ni in the alloy affects the microstructure and composition, the morphology of the metal/GaAs interface, and the amount of GaAs consumed during the alloy reaction. Also, the dopant distribution into the GaAs is heterogeneous depending on the alloy microstructure.

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