Process Design & Integration of Salicide and Source/Drain process Modules for Improved Device Performance

1998 ◽  
Vol 514 ◽  
Author(s):  
Pushkar P. Apte ◽  
Shared Saxena ◽  
Suraj Rao ◽  
Karthik Vasanth ◽  
Douglas A. Prinslow ◽  
...  
Keyword(s):  
Process Design ◽  
Doping Concentration ◽  
Channel Length ◽  
Process Conditions ◽  
Circuit Performance ◽  
Physical Mechanisms ◽  
Substrate Current ◽  
Design Integration ◽  
Circuit Delays ◽  
Dopant Redistribution

ABSTRACTTo enable swift integration of process modules into manufacturable process flows; three components – individual process modules, their interactions and their variability-must be understood well. At dimensions ≤ 0.25 μm, this understanding is especially critical, and also quite challenging. We present here an approach to address this challenge by joint process design, using two key modules-salicide and source/drain-as an example. Together, these modules impact the silicide-to-diffusion contact resistance, (Rc), and the gate sheet resistance (Rs); which, in turn, significantly affect transistor series resistance and circuit delays respectively. We have built a model to help provide insight into the underlying physical mechanisms, and to help provide a quantitative framework for optimizing performance and variability. Rc, depends critically on the doping concentration immediately adjacent to the silicide, and this concentration is determined by the combined effect of silicide processing and the two-dimensional source/drain dopant profile. Rs depends on the thickness and phase of the silicide film formed, which, in turn, depend on the salicide process variables as well as the source/drain doping concentration, because both affect the silicide growth kinetics. Process conditions favoring Rs. and Rc are opposite to each other: thicker silicide films and higher thermal budgets help in the phase-transformation to the low-resistivity C54 phase and improve Rs but they increase dopant redistribution and worsen Rc. Optimal process design can improve the transistor drive current (Id) by ≈5%, and circuit performance, as measured by the figure-of-merit (FOM) by ≈ 4%. This improvement is significant, and an added benefit of this approach is that other transistor characteristics such as effective channel length, off-current, substrate current, etc. remain unchanged. In summary, we have demonstrated that by joint process design and integration of the salicide and source/drain modules, insight can be gained into the underlying physical mechanisms, and device and circuit performance can be improved significantly.

Process Design & Integration of Salicide and Source/Drain Process Modules for Improved Device Performance

1998 ◽  
Vol 525 ◽  
Author(s):  
Pushkar P. Apte ◽  
Sharad Saxena ◽  
Suraj Rao ◽  
Karthik Vasanth ◽  
Douglas A. Prinslow ◽  
...  
Keyword(s):  
Process Design ◽  
Integrated Circuit ◽  
High Performance ◽  
Performance Enhancement ◽  
Process Integration ◽  
Channel Length ◽  
Trade Offs ◽  
Design Integration ◽  
And Performance ◽  
Circuit Delays

ABSTRACTIn integrated circuit (IC) fabrication, understanding and optimizing process interactions and variability is critical for swift process integration and performance enhancement, especially at dimensions ≤0.25μm. We present here an approach to address this challenge, and we apply it to improve the process design for two critical modules in a typical CMOS IC process—salicide and source/drain. Together, these modules impact the silicide-to-diffusion contact resistance (Rc), and the gate sheet resistance (Rs); which, in turn, significantly affect transistor series resistance and circuit delays respectively. In our approach, we have investigated a process domain consisting of both silicide and source/drain process variables; and we have developed a quantitative framework for analysis and optimization, along with qualitative insight into underlying the physical mechanisms. We demonstrate that the transistor drive current (Id) improves by ≈5‥, and circuit performance, as measured by the figure-of-merit (FOM), by ≈4‥. This improvement is significant, and an added benefit is that other transistor characteristics such as effective channel length, off-current, substrate current etc. are affected minimally. Finally, we use this approach to optimize trade-offs such as Rc vs Rs and performance vs manufacturability; thus enabling manufacturable processes that meet the requirements for high performance.

Current-Signature-Based Analysis of Complex Test Fails

1999 ◽  
Author(s):  
Anne E. Gattiker ◽  
Phil Nigh ◽  
Wojciech Maly
Keyword(s):  
Failure Analysis ◽  
Physical Nature ◽  
Channel Length ◽  
Test Methods ◽  
Multiple Test ◽  
Physical Mechanisms ◽  
Test Behavior ◽  
Complex Test ◽  
Current Signature ◽  
Insight Into

Abstract This article provides an analysis of a class of failures observed during the SEMATECH-sponsored Test Methods Experiment. The analysis focuses on use of test-based failure analysis and IDDQ signature analysis to gain insight into the physical mechanisms underlying such subtle failures. In doing so, the analysis highlights techniques for understanding failure mechanisms using only tester data. In the experiment, multiple test methods were applied to a 0.45 micrometer effective channel length ASIC. Specifically, ICs that change test behavior from before to after burn-in are studied to understand the physical nature of the mechanism underlying their failure. Examples of the insights provided by the test-based analysis include identifying cases where there are multiple or complex defects and distinguishing cases where the defect type is likely to be a short versus an open and determining if the defect is marginal. These insights can be helpful for successful failure analysis.

Hot Carrier Effects in Deep Submicron Nmosfets

1996 ◽  
Vol 428 ◽  
Author(s):  
Abhijit Phanse ◽  
Samar Saha
Keyword(s):  
Electric Fields ◽  
Channel Length ◽  
Deep Submicron ◽  
Short Channel ◽  
Hot Carrier ◽  
Velocity Saturation ◽  
Substrate Current ◽  
Hot Carrier Effects ◽  
Saturation Effects ◽  
Channel Lengths

AbstractThis paper addresses hot-carrier related reliability issues in deep submicron silicon nMOSFET devices. In order to monitor the hot-carrier induced device degradation, the substrate current was measured for devices with varying channel lengths (20 um - 0.24 um) under various biasing conditions. Deep submicron devices experience velocity saturation of channel carriers due to extremely high lateral electric fields. To evaluate the effects of velocity saturation in the channel, the pinch-off length in the channel was extracted for all the devices of the target technology. It was observed that for very short channel devices, carriers in most of the channel experience velocity saturation and almost the entire channel gets pinched off. It is shown in this paper that for very short channel devices, the pinch-off length in the channel is limited by the effective channel length, and that velocity saturation effects are critical to the transport of channel carriers.

scholarly journals The Effect of Doping on Different FET Structures: MOSFET, TFET and FinFET

2020 ◽  
Vol 9 (6) ◽  
pp. 972-979
Keyword(s):  
Drain Current ◽  
Channel Length ◽  
Short Channel Effects ◽  
Poor Control ◽  
Short Channel ◽  
Circuit Performance ◽  
The Past ◽  
Channel Effects ◽  
Circuit Density ◽  
Effect Of Doping

MOSFET have been scaled down over the past few years in order to give rise to high circuit density and increase the speed of circuit. But scaling of MOSFET leads to issues such as poor control gate over the current which depends on gate voltage. Many short channel effects (SCE) influence the circuit performance and leads to the indeterminist response of drain current. These effects can be decreased by gate excitation or by using multiple gates and by offering better control gate the device parameters. In Single gate MOSFET, gate electric field decreases but multigate MOSFET or FinFET provides better control over drain current. In this paper, different FET structures such as MOSFET, TFET and FINFET are designed at 22nm channel length and effect of doping had been evaluated and studied. To evaluate the performance donor concentration is kept constant and acceptor concentration is varied.

Design and Gate Drive Considerations for Epitaxial 1.2 kV Buried Grid N-on and N-off JFETs for Operation at 250°C

2010 ◽  
Vol 645-648 ◽  
pp. 961-964 ◽  
Author(s):  
Jang Kwon Lim ◽  
Mietek Bakowski ◽  
Hans Peter Nee
Keyword(s):  
Threshold Voltage ◽  
Doping Concentration ◽  
Channel Length ◽  
Channel Width ◽  
Temperature Range ◽  
Turn On ◽  
Switching Losses ◽  
Order Of Magnitude ◽  
Gate Resistance

The 1.2 kV 4H-SiC buried-grid vertical JFET structures with Normally-on (N-on) and Normally-off (N-off) design were investigated by simulations. The conduction and switching properties were determined in the temperature range from -50°C to 250°C. In this paper, the characteristics of the N-on designs with threshold voltage (Vth) of -50 V and -10 V are compared with the N-off design (Vth=0). The presented data are for devices with the same channel length at 250°C. The results show that the on-resistance (Ron) decreases with increasing channel doping concentration and decreasing channel width. The presented turn-on, Eon, and turn-off, Eoff, energies per pulse are calculated under the switching conditions 100 A/cm2 and 600 V with a gate resistance of Rg=1 . For the two N-on designs the total switching losses, Esw=Eon+Eoff, differ less than 30% with Wch 0.7 m. With Wch=0.5 m the switching losses of N-off design are almost one order of magnitude higher than those of the N-on design with Vth = -50 V.

scholarly journals Process Design, Development and Mechanical Analysis of Cu-Zn Alloy Produced by Sand Casting Process

2021 ◽  
Author(s):  
Ilesanmi Afolabi Daniyan ◽  
Adefemi Adeodu ◽  
Oluwaseun Alo ◽  
Bankole Oladapo
Keyword(s):  
Tensile Strength ◽  
Ultimate Tensile Strength ◽  
Process Design ◽  
Copper Wire ◽  
Zinc Content ◽  
Casting Process ◽  
Mechanical Analysis ◽  
Sand Casting ◽  
Process Conditions ◽  
Design Development

Abstract In this study, the process design, development and mechanical analysis of Cu-Zn alloy produced by sand casting process were carried out. The process parameter optimization was carried out using the Response Surface Methodology (RSM) with the process conditions in the following range: temperature (300-500oC) and zinc content (5-25%) having the hardness and ultimate tensile strength as the response of the designed experiment. The raw materials were scraps of copper wire and zinc battery casing and 13 different compositions of the alloy were prepared having the total mass for each weight percentage weighing 1.5 kg. The results obtained indicated that the hardness and ultimate tensile strength increases with an increases in the zinc content but decreases with an increase in the temperature. The elongation was however found to increase with an in increase in temperature but with a decrease in the zinc content. It is envisaged that the findings of this work will assist the brass material developers and the end users in the development of products with excellent mechanical properties.

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