‘Back end’ Chemical Cleaning in integrated Circuit Fabrication: a Tutorial

1997 ◽  
Vol 477 ◽  
Author(s):  
Yaw S. Obeng ◽  
R. S. Raghavan
Keyword(s):  
Integrated Circuit ◽  
Management Strategies ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Chemical Processing ◽  
Chemical Cleaning ◽  
Barrier Films ◽  
Integrated Circuit Fabrication ◽  
Circuit Fabrication ◽  
Wet Chemical

ABSTRACTThe applications of wet chemical cleaning at the ‘back-end’ of Integrated Circuit (IC) or Metal-Oxide Semiconductor (MOS) fabrication are reviewed from chemical, environmental and cost perspectives. The various classes of commercially available “solvents” and “cryogenic” cleans are reviewed from the perspective of process suitability, impact on device yield and waste management. Strategies for minimizing processing concerns, as well as alternatives to organic solvent based wet chemical processing will also be discussed. Bulk photoresist (PR) stripping, post metal definition-, and post window etch cleaning are used to illustrate the discussion.The use of radiotracing as a diagnostic tool in understanding the mechanism for metallic contamination during solvent cleans is also discussed. Data suggesting how the chemistry and solvent composition affects alkali metal (for example, sodium) contamination of dielectric- and barrier films during IC processing will also be presented.

Evolution of Stress During Formation of Titanium Disilicide by Rta and Tube Furnace Annealing

1990 ◽  
Vol 202 ◽  
Author(s):  
J.F. Jongste ◽  
O.B. Loopstra ◽  
G.C.A.M. Janssen ◽  
S. Radelaar
Keyword(s):  
Integrated Circuit ◽  
Thermal Processing ◽  
Reaction Rates ◽  
Titanium Disilicide ◽  
Furnace Annealing ◽  
Integrated Circuit Fabrication ◽  
Annealing Step ◽  
Circuit Fabrication ◽  
The Difference ◽  
Processing Steps

Integrated circuit fabrication consists of many processing steps: e.g. lithography, etching, implantation and metallization. Some of these processes are combined with thermal processing. Heat treatments require special attention because previous fabrication steps may be influenced: e.g. dopant profiles may be deteriorated. The amount of interference of an annealing step with a former process is determined by the ratio of the reaction rates (and hence by the difference in activation energies).

A Fresh Insight into Film Morphology Measurement Techniques for Advanced Ulsi Manufacturing

1993 ◽  
Vol 309 ◽  
Author(s):  
Seshadri Ramaswami
Keyword(s):  
Grain Size ◽  
Integrated Circuit ◽  
Measurement Techniques ◽  
Film Morphology ◽  
Integrated Circuit Fabrication ◽  
Circuit Fabrication ◽  
Non Destructive ◽  
Fresh Insight ◽  
Insight Into

AbstractA laser based non-destructive technique has been used to study the morphology of sputterdeposited aluminum alloy films. The data emanating from the Therma-wave Imager that makes use of this principle, has been correlated with reflectivity, grain size and micro-roughness of the film. In addition, through the use of a case study, this paper demonstrates the utility of this application as an in-line monitor in an integrated circuit fabrication line.

Silicon Rapid Thermal Processing with Ripple Pyrometry

1997 ◽  
Vol 502 ◽  
Author(s):  
A. T. Fiory
Keyword(s):  
Integrated Circuit ◽  
Thermal Processing ◽  
Wide Field ◽  
Loop Control ◽  
Dopant Activation ◽  
Integrated Circuit Fabrication ◽  
Metal Silicides ◽  
Circuit Fabrication ◽  
Infrared Lamps

ABSTRACTThermal processing in silicon integrated circuit fabrication steps for dopant activation, metal silicides, annealing, and oxidation commonly uses single-wafer furnaces that rapidly heat wafers with incandescent infrared lamps. Radiation pyrometers and thermocouple probes are the principle methods of measuring wafer temperature for closed-loop control of rapid thermal processes. The challenge with thermocouples is in dealing with heat from the lamps and non-ideal thermally resistive wafer contact. The challenge with pyrometry is in compensating for the variable emissivity of wafer surfaces and suppressing interference from the lamps. Typical deposited or grown layers of silicon nitride, silicon dioxide, and polycrystalline silicon can produce dramatic changes in emissivity. Layer thicknesses and composition are generally not known with sufficient accuracy, so a method for real time in situ emissivity compensation is required. Accufiber introduced a “ripple technique” to address this issue. The idea is to use two probes, separately sensing radiation from the wafer and the lamps, and extracting AC and quasi-DC parts from each. The AC signals provide a measure of the reflectivity of the wafer, and thence emissivity, as well as the fraction of reflected lamp radiation present in the DC signals. Lucent Technologies introduced a method of using AC lamp ripple to measure wafer temperatures with two radiation probes at a wall in the furnace. One probe views radiation emanating from the wafer through a gap in the lamp array. The other probe has a wide field of view to include lamp radiation. The accuracy of Lucent devices, determined from process results on wafers with various emissivities, is typically in the range of 12°C to 18°C at three standard deviations.

scholarly journals Effects of Process Variations in a HCMOS IC using a Monte Carlo SPICE Simulation

2017 ◽  
pp. 11-16
Author(s):  
Widianto Widianto ◽  
Lailis Syafaah ◽  
Nurhadi Nurhadi
Keyword(s):  
Monte Carlo ◽  
Integrated Circuit ◽  
High Speed ◽  
Evaluation Method ◽  
Complementary Metal Oxide Semiconductor ◽  
Process Variations ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Spice Simulation ◽  
Simulation Results

In this paper, effects of process variations in a HCMOS (High-Speed Complementary Metal Oxide Semiconductor) IC (Integrated Circuit) are examined using a Monte Carlo SPICE (Simulation Program with Integrated Circuit Emphasis) simulation. The variations of the IC are L and VTO variations. An evaluation method is used to evaluate the effects of the variations by modeling it using a normal (Gaussian) distribution. The simulation results show that the IC may be detected as a defective IC caused by the variations based on large supply currents flow to it. 

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