A Defect Map for Degradation of Ingaasp/Inp Long Wavelength Laser Diodes

1996 ◽  
Vol 421 ◽  
Author(s):  
S.N.G. Chu ◽  
S. Nakahara

AbstractWe summarize the characteristic defect structures associated with gradual-degradation, rapiddegradation, catastrophic (mirror-facet) optical damage (COD), electric static discharge (ESD) and electric overstress (EOS) damages to provide a defect-map for device failure mode analysis. The generation mechanisms of these lattice defects are discussed which pinpoint the weak links in the device structures.

2018 ◽  
Vol 39 (2) ◽  
pp. 180-187
Author(s):  
刘启坤 LIU Qi-kun ◽  
孔金霞 KONG Jin-xia ◽  
朱凌妮 ZHU Ling-ni ◽  
熊聪 XIONG Cong ◽  
刘素平 LIU Su-ping ◽  
...  

2002 ◽  
Author(s):  
Robert G. Ahrens ◽  
James J. Jaques ◽  
Niloy K. Dutta ◽  
Michael J. LuValle ◽  
Alfonso B. Piccirilli ◽  
...  

2013 ◽  
pp. 1361-1368
Author(s):  
Frederick J. Schoen ◽  
Allan S. Hoffman

2003 ◽  
Author(s):  
Aland K. Chin ◽  
Zhiping Wang ◽  
Kejian Luo ◽  
Alan Nelson ◽  
Zuntu Xu

Author(s):  
R. Sharma ◽  
B.L. Ramakrishna ◽  
N.N. Thadhani ◽  
D. Hianes ◽  
Z. Iqbal

After materials with superconducting temperatures higher than liquid nitrogen have been prepared, more emphasis has been on increasing the current densities (Jc) of high Tc superconductors than finding new materials with higher transition temperatures. Different processing techniques i.e thin films, shock wave processing, neutron radiation etc. have been applied in order to increase Jc. Microstructural studies of compounds thus prepared have shown either a decrease in gram boundaries that act as weak-links or increase in defect structure that act as flux-pinning centers. We have studied shock wave synthesized Tl-Ba-Cu-O and shock wave processed Y-123 superconductors with somewhat different properties compared to those prepared by solid-state reaction. Here we report the defect structures observed in the shock-processed Y-124 superconductors.


Author(s):  
Martin Versen ◽  
Dorina Diaconescu ◽  
Jerome Touzel

Abstract The characterization of failure modes of DRAM is often straight forward if array related hard failures with specific addresses for localization are concerned. The paper presents a case study of a bitline oriented failure mode connected to a redundancy evaluation in the DRAM periphery. The failure mode analysis and fault modeling focus both on the root-cause and on the test aspects of the problem.


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