The Merits of Integrated Processing for Gate Stack Formation

1995 ◽  
Vol 387 ◽  
Author(s):  
John M. Grant
Keyword(s):  
Vapor Phase ◽  
Process Development ◽  
Nitrogen Concentration ◽  
Chemical Vapor ◽  
Electrical Performance ◽  
Gate Stack ◽  
Integrated Processing ◽  
Oxide Substrate ◽  
Wafer Processing ◽  
Cluster Tool

AbstractThis work presents the results of process development in a cluster tool designed for the gate stack process of cleaning, gate oxidation, and polysilicon chemical vapor deposition. The cluster tool connects three single wafer process chambers together with a vacuum transfer chamber. The purpose of this work was to test the feasibility of the single wafer processing gate oxidation cluster tool from an electrical performance standpoint, Cleaning was performed using a gas/vapor phase process, and the results using a standard oxide indicate that gas/vapor phase cleaning is at the least comperable and possibly more effective at contamination removal than the standard RCA wet cleaining process. The oxidation was performed using rapid thermal processing, and the effect of adding nitrogen to the oxide by oxidation in an N2O containing ambient was tested. The results indicated that oxides at least at good as those grown in a conventional furnace could be produced in the cluster tool, and the nitrogen at the oxide-substrate interface improves the reliability of the oxide if the nitrogen concentration is kept below 1 atomic %.

Integrated Vapor Phase Cleaning and Pure no Nitridation for Gate Stack Formation

1997 ◽  
Vol 470 ◽  
Author(s):  
F. Glowacki ◽  
B. Froeschle ◽  
L. Deutschmann ◽  
I. Sagnes ◽  
D. Laviale ◽  
...  
Keyword(s):  
Chemical Vapor Deposition ◽  
Vapor Phase ◽  
Vapor Deposition ◽  
Process Development ◽  
Chemical Vapor ◽  
Gate Stack ◽  
Wafer Processing ◽  
First Time ◽  
Cluster Tool ◽  
Insight Into

ABSTRACTThe purpose of this publication is to give an insight into process development performed in two modules which belong to a cluster tool designed for the gate stack process sequence of cleaning, gate oxidation, and polysilicon chemical vapor deposition. For the first time, following the hardware and software MESC-based standards, two suppliers have integrated complementary modules to build a cluster tool. This equipment answers the demands of the 1C Manufacturers and follows the “best of breed” approach. Four single wafer rapid thermal process chambers, a Vapor Phase Cleaning (VPC) and a Rapid Thermal Oxidation/Nitridation (RTO/N) module from STEAG-AST Elektronik, a polysilicon and a nitride chemical vapor deposition module from ASM International are currently connected together to prove the feasibility of the single wafer processing gate stack cluster tool.

Integrated Rapid Thermal CVD Processing Solutions for 0.18–0.25μm Technologies

1997 ◽  
Vol 470 ◽  
Author(s):  
H. Gilboa ◽  
Y. E. Gilboa ◽  
Z. Atzmon ◽  
S. Levy ◽  
H. Spilberg ◽  
...  
Keyword(s):  
High Temperature ◽  
Flash Memory ◽  
Thermal Processing ◽  
Rapid Thermal Processing ◽  
Chemical Vapor ◽  
Wafer Cleaning ◽  
Front End ◽  
Wafer Processing ◽  
Cluster Tool ◽  
Temperature Applications

ABSTRACTThe evolution of integrated single-wafer processing for high-temperature applications in the front end of the line (FEOL) occurred with the advancements in single-wafer rapid thermal processing and its acceptance as a manufacturing technology. The Integra RTCVD cluster tool for high-temperature applications features wafer cleaning, rapid thermal processing and single wafer chemical vapor deposition steps. The paper presents integrated vapor phase clean and RTCVD applications for FLASH memory gate stack and DRAM cell.

Metal Microstructures in Advanced CMOS Devices

1996 ◽  
Vol 54 ◽  
pp. 358-359
Author(s):  
L. M. Gignac ◽  
K. P. Rodbell
Keyword(s):  
Grain Boundaries ◽  
Semiconductor Device ◽  
Chemical Vapor ◽  
Microstructural Characterization ◽  
Metal Films ◽  
Thin Metal ◽  
Electrical Performance ◽  
Thin Metal Films ◽  
Chemical Vapor Deposited ◽  
Boundary Properties

As advanced semiconductor device features shrink, grain boundaries and interfaces become increasingly more important to the properties of thin metal films. With film thicknesses decreasing to the range of 10 nm and the corresponding features also decreasing to sub-micrometer sizes, interface and grain boundary properties become dominant. In this regime the details of the surfaces and grain boundaries dictate the interactions between film layers and the subsequent electrical properties. Therefore it is necessary to accurately characterize these materials on the proper length scale in order to first understand and then to improve the device effectiveness. In this talk we will examine the importance of microstructural characterization of thin metal films used in semiconductor devices and show how microstructure can influence the electrical performance. Specifically, we will review Co and Ti silicides for silicon contact and gate conductor applications, Ti/TiN liner films used for adhesion and diffusion barriers in chemical vapor deposited (CVD) tungsten vertical wiring (vias) and Ti/AlCu/Ti-TiN films used as planar interconnect metal lines.

Solvent-Free Powder Synthesis and MOF-CVD Thin Films of the Mesoporous Metal-Organic Framework MAF-6

2019 ◽  
Author(s):  
Timothée Stassin ◽  
Ivo Stassen ◽  
Joao Marreiros ◽  
Alexander John Cruz ◽  
Rhea Verbeke ◽  
...  
Keyword(s):  
Vapor Phase ◽  
Metal Organic Framework ◽  
Chemical Vapor ◽  
Uptake Capacity ◽  
Powder Synthesis ◽  
Crystalline Films ◽  
Metal Organic ◽  
Mesoporous Metal ◽  
First Time ◽  
Organic Framework

A simple solvent- and catalyst-free method is presented for the synthesis of the mesoporous metal-organic framework (MOF) MAF-6 (RHO-Zn(eIm)2) based on the reaction of ZnO with 2-ethylimidazole vapor at temperatures ≤ 100 °C. By translating this method to a chemical vapor deposition (CVD) protocol, mesoporous crystalline films could be deposited for the first time entirely from the vapor phase. A combination of PALS and Kr physisorption measurements confirmed the porosity of these MOF-CVD films and the size of the MAF-6 supercages (diam. ~2 nm), in close agreement with powder data and calculations. MAF-6 powders and films were further characterized by XRD, TGA, SEM, FTIR, PDF and EXAFS. The exceptional uptake capacity of the mesoporous MAF-6 in comparison to the microporous ZIF-8 is demonstrated by vapor-phase loading of a molecule larger than the ZIF-8 windows.

Nitrogen (N2) Implantation to Suppress Growth of Interfacial Oxide in Mocvd Bst and Sputtered Bst Films

1999 ◽  
Vol 567 ◽  
Author(s):  
Renee Nieh ◽  
Wen-Jie Qi ◽  
Yongjoo Jeon ◽  
Byoung Hun Lee ◽  
Aaron Lucas ◽  
...  
Keyword(s):  
Photoelectron Spectroscopy ◽  
Interfacial Layer ◽  
Gate Dielectric ◽  
Nitrogen Concentration ◽  
Chemical Vapor ◽  
Future Generation ◽  
Oxide Thickness ◽  
Layer Growth ◽  
X Ray ◽  
Bst Films

ABSTRACTBa0.5Sr0.5TiO3 (BST) is one of the high-k candidates for replacing SiO2 as the gate dielectric in future generation devices. The biggest obstacle to scaling the equivalent oxide thickness (EOT) of BST is an interfacial layer, SixOy, which forms between BST and Si. Nitrogen (N2) implantation into the Si substrate has been proposed to reduce the growth of this interfacial layer. In this study, capacitors (Pt/BST/Si) were fabricated by depositing thin BST films (50Å) onto N2 implanted Si in order to evaluate the effects of implant dose and annealing conditions on EOT. It was found that N2 implantation reduced the EOT of RF magnetron sputtered and Metal Oxide Chemical Vapor Deposition (MOCVD) BST films by ∼20% and ∼33%, respectively. For sputtered BST, an implant dose of 1×1014cm−;2 provided sufficient nitrogen concentration without residual implant damage after annealing. X-ray photoelectron spectroscopy data confirmed that the reduction in EOT is due to a reduction in the interfacial layer growth. X-ray diffraction spectra revealed typical polycrystalline structure with (111) and (200) preferential orientations for both films. Leakage for these 50Å BST films is on the order of 10−8 to 10−5 A/cm2—lower than oxynitrides with comparable EOTs.

Growth of epitaxial sodium-bismuth-titanate films by metal-organic chemical vapor phase deposition

2011 ◽  
Vol 520 (1) ◽  
pp. 239-244 ◽  
Author(s):  
J. Schwarzkopf ◽  
M. Schmidbauer ◽  
A. Duk ◽  
A. Kwasniewski ◽  
S. Bin Anooz ◽  
...  
Keyword(s):  
Vapor Phase ◽  
Bismuth Titanate ◽  
Chemical Vapor ◽  
Organic Chemical ◽  
Sodium Bismuth Titanate ◽  
Vapor Phase Deposition ◽  
Metal Organic

Mocvd SrS:Ce for Applications in Electroluminescent Devices

1997 ◽  
Vol 471 ◽  
Author(s):  
D. Endisch ◽  
K. Barth ◽  
J. Lau ◽  
G. Peterson ◽  
A. E. Kaloyeros ◽  
...  
Keyword(s):  
Process Development ◽  
Process Integration ◽  
Low Cost ◽  
Chemical Vapor ◽  
High Growth ◽  
Film Structure ◽  
High Growth Rate ◽  
Organic Chemical ◽  
Glass Substrates ◽  
Full Color

ABSTRACTSrS:Ce is an important material for full color electroluminescent (EL) flat panel displays. Using a combination of SrS:Ce/ZnS:Mn and appropriate color filters high quality full color displays have been demonstrated [1]. Major issues for commercially viable process integration of SrS:Ce are the combination of high luminance, high growth rate, and process temperatures below 600°C for compatibility with low cost glass substrates. This work describes the process development and optimization of metal-organic chemical vapor deposition (MOCVD) of SrS:Ce. MOCVD is a promising candidate for deposition of SrS:Ce because it can provide the required growth rates and allows control of crystal structure and stoichiometry. Growth of SrS:Ce was performed in the temperature range from 400°C to 530°C using Sr(tmhd)2, Ce(tmhd)4, and H2S as precursors. The structure of the SrS:Ce was found to be strongly dependent on the H2S flow. A brightness of 15 fL and an efficiency of 0.22 lm/W has been achieved (40 V above threshold voltage, 60 Hz AC). Film analysis included Rutherford backscattering (RBS), X-ray diffraction (XRD), atomic force microscopy (AFM), and EL measurements. Results on the correlation between process parameters, film structure, grain size and EL performance will be presented.

scholarly journals Correction: Self-supported Co3O4 nanoneedle arrays decorated with PPy via chemical vapor phase polymerization for high-performance detection of trace Pb2+

2017 ◽  
Vol 9 (16) ◽  
pp. 2472-2472 ◽  
Author(s):  
Wenjing Wang ◽  
Chao Wang ◽  
Peng Dou ◽  
Lifang Zhang ◽  
Jiao Zheng ◽  
...  
Keyword(s):  
Vapor Phase ◽  
High Performance ◽  
Chemical Vapor ◽  
Vapor Phase Polymerization

Correction for ‘Self-supported Co3O4 nanoneedle arrays decorated with PPy via chemical vapor phase polymerization for high-performance detection of trace Pb2+’ by Wenjing Wang et al., Anal. Methods, 2017, 9, 1905–1911.

Probing the metal gate high k interactions by backside XPS and C-AFM

2011 ◽  
Vol 1336 ◽  
Author(s):  
U. Celano ◽  
T. Conard ◽  
T. Hantschel ◽  
W. Vandervorst
Keyword(s):  
Ion Beam ◽  
Electrical Performance ◽  
Ion Beam Sputtering ◽  
Metal Gate ◽  
Gate Stack ◽  
Conductive Atomic Force Microscopy ◽  
Characterization Methods ◽  
Force Microscopy ◽  
High K ◽  
Beam Sputtering

ABSTRACTThe metal gate high k interaction is one of the dominant processes influencing the electrical performance (Vt, charge accumulation,..) of advanced gate stacks. These interactions are influenced by the entire thermal budget and the presence of reactive elements (on top/ within the material gate) such that relevant measurements can only be performed after a full processing cycle and on a complete gate stack.In such cases the relevant metal gate high k interface is a buried interface located below the metal gate (+ Si cap) and is not accessible for standard characterization methods like x-ray photoemission spectroscopy (XPS) due the limited escape depth of the photoelectrons. Moreover the presence of a conductive metal gate prevents the application of techniques such as conductive atomic force microscopy (C-AFM), to probe the local distribution of the defects, trapping sites and local degradation upon stressing. XPS in combination with layer removal steps like ion beam sputtering will destroy the bonding information and is thus not applicable. Chemical etching of the metal gate stack prior to the XPS measurements requires an extremely precious control of the etching in order to stop 1-2 nm before the high k metal interface.As an alternative we have developed a backside removal approach, that allows us to investigate using techniques such as XPS and C-AFM, the metal gate high k interface.

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