The Formation of Defects Degrading Gate Oxide Integrity During CZ-Si Crystal Growth

1995 ◽  
Vol 378 ◽  
Author(s):  
Y. Tsumori ◽  
K. Nakai ◽  
T. Iwasaki ◽  
H. Haga ◽  
K. Kojima ◽  
...  
Keyword(s):  
Crystal Growth ◽  
Point Defects ◽  
Defect Density ◽  
Gate Oxide ◽  
Cooling Time ◽  
Intrinsic Point Defects ◽  
Pair Annihilation ◽  
Temperature Ranges ◽  
Gate Oxide Integrity

AbstractThe formation of grown-in defects degrading the gate oxide integrity (GOI) has been studied. The growth-halting experiments were carried out to investigate the temperature ranges at which the formation of the defects was promoted or suppressed. GOI is improved in the crystal regions slowly cooled above 1330°C and between 1060°C and 1100°C. It is degraded in the crystal regions held below 1060°C. In the peripheral of the crystals, those temperature ranges are about 30°C lower. The defects are formed and grown below 1060°C in the center part of the crystal. The defect density is decreased with cooling time between 1060°C and 1100°C. These phenomena are considered to be closely related with reactions of intrinsic point defects, that is, the pair annihilation or the aggregation. The temperatures at which the pair annihilation and the aggregation of the point defects occur are dependent upon the supersaturation of the point defects.

A New Failure Analysis Flow of Gate Oxide Integrity Failure in Wafer Fabrication

2009 ◽  
Author(s):  
Hua Younan ◽  
Chu Susan ◽  
Gui Dong ◽  
Mo Zhiqiang ◽  
Xing Zhenxiang ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Gate Dielectric ◽  
Dielectric Breakdown ◽  
Defect Density ◽  
Gate Oxide ◽  
Oxide Thickness ◽  
Fault Isolation ◽  
Wafer Fabrication ◽  
Root Cause ◽  
Gate Oxide Integrity

Abstract As device feature size continues to shrink, the reducing gate oxide thickness puts more stringent requirements on gate dielectric quality in terms of defect density and contamination concentration. As a result, analyzing gate oxide integrity and dielectric breakdown failures during wafer fabrication becomes more difficult. Using a traditional FA flow and methods some defects were observed after electrical fault isolation using emission microscopic tools such as EMMI and TIVA. Even with some success with conventional FA the root cause was unclear. In this paper, we will propose an analysis flow for GOI failures to improve FA’s success rate. In this new proposed flow both a chemical method, Wright Etch, and SIMS analysis techniques are employed to identify root cause of the GOI failures after EFA fault isolation. In general, the shape of the defect might provide information as to the root cause of the GOI failure, whether related to PID or contamination. However, Wright Etch results are inadequate to answer the questions of whether the failure is caused by contamination or not. If there is a contaminate another technique is required to determine what the contaminant is and where it comes from. If the failure is confirmed to be due to contamination, SIMS is used to further determine the contamination source at the ppm-ppb level. In this paper, a real case of GOI failure will be discussed and presented. Using the new failure analysis flow, the root cause was identified to be iron contamination introduced from a worn out part made of stainless steel.

Intrinsic Point Defects in Silicon Crystal Growth

2011 ◽  
Vol 178-179 ◽  
pp. 3-14 ◽  
Author(s):  
Vladimir V. Voronkov ◽  
Robert Falster
Keyword(s):  
Crystal Growth ◽  
Point Defects ◽  
Vacancy Concentration ◽  
Silicon Crystal ◽  
Growth Conditions ◽  
Intrinsic Point Defects ◽  
Silicon Crystals ◽  
Low Concentrations ◽  
Different Populations ◽  
Vacancy Concentrations

In dislocation-free silicon, intrinsic point defects – either vacancies or self-interstitials, depending on the growth conditions - are incorporated into a growing crystal. Their incorporated concentration is relatively low (normally, less than 1014 cm-3 - much lower than the concentration of impurities). In spite of this, they play a crucial role in the control of the structural properties of silicon materials. Modern silicon crystals are grown mostly in the vacancy mode and contain many vacancy-based agglomerates. At typical grown-in vacancy concentrations the dominant agglomerates are voids, while at lower vacancy concentrations there are different populations of joint vacancy-oxygen agglomerates (oxide plates). Larger plates – formed in a narrow range of vacancy concentration and accordingly residing in a narrow spatial band – are responsible for the formation of stacking fault rings in oxidized wafers. Using advanced crystal growth techniques, whole crystals can be grown at such low concentrations of vacancies or self-interstitials such that they can be considered as perfect.

Dependence of gate oxide integrity on grown-in defect density in Czochralski grown silicon

1999 ◽  
Vol 48 (1-4) ◽  
pp. 127-130 ◽  
Author(s):  
U. Lambert ◽  
A. Huber ◽  
J. Grabmeier ◽  
G. Obermeier ◽  
J. Vanhellemont ◽  
...  
Keyword(s):  
Defect Density ◽  
Gate Oxide ◽  
Gate Oxide Integrity

Effects of Silicon Ion Implantation upon Thin Gate Oxide Integrity

1992 ◽  
Vol 262 ◽  
Author(s):  
G. -S. Lee ◽  
J. -G. Park ◽  
S. -P. Choi ◽  
C. -H. Shin ◽  
Y. -B. Sun ◽  
...  
Keyword(s):  
Ion Implantation ◽  
Dielectric Breakdown ◽  
Defect Density ◽  
Surface Region ◽  
Gate Oxide ◽  
Near Surface ◽  
Time Dependent Dielectric Breakdown ◽  
Thin Gate Oxide ◽  
Si Ion Implantation ◽  
Gate Oxide Integrity

ABSTRACTIn this study, using oxide breakdown voltage and time-dependent-dielectric breakdown measurements, thermal wave modulated reflectance and chemical etching/optical microscopy, we investigated effects of Si ion implantation upon formation of D-defects and thin gate oxide integrity. Our data show that addition of Si ion implantation with a dose of up to 1013 ions/cm2 improves oxide integrity if the implantation is done at a certain step just before sacrificial oxidation in the Mb DRAM process. However, no improvement in oxide integrity is observed when the same implantation is done on the virgin wafer surfaces at the start of the same Mb DRAM process. We discuss our hypothesis that the improvement in oxide integrity is due to a reduction in the D-defect density in the near-surface region of the wafer.

Sign in / Sign up

Export Citation Format

Share Document