Self-Aligned Epitaxial Cosi2 Formation From Multilayer Co/Ti-Si(100) by a Two-Step Rta Process

1993 ◽  
Vol 303 ◽  
Author(s):  
F. Hong ◽  
B.K. Patnaik ◽  
G.A. Rozgonyi ◽  
C.M. Osburn
Keyword(s):  
Surface Layer ◽  
Thermal Oxidation ◽  
Recent Work ◽  
Amorphous Layer ◽  
Deep Submicron ◽  
Annealing Process ◽  
Thermally Stable ◽  
Si Substrates ◽  
Nano Scale ◽  
Patterned Wafers

ABSTRACTWe have extended our recent work on nano-scale CoSi2 formation from Co/Ti(O)multilayers on Si(100) to a self-aligned epitaxial CoSi2 structure produced by a two-step RTA annealing process. Parallel oxide stripes/Si windows were produced on a 4-inch Si(100) wafer by thermal oxidation and patterning. Six layers of 20nm Co and 10nm Ti were deposited sequentially on the patterned wafers with Ti as the first layer. The wafers were then annealed at 550°C to 700°C in N2 using a lamp RTA system. XTEM and RBS showed that a 25nm CoSi layer formed at the interface after a 650°C, 60sec annealing. The unreacted layers above it and oxide were selectively removed leaving a residual amorphous layer and CoSi intact on the patterned Si substrates. A second annealing at 900'C for 10sec produced 20nm of epitaxial CoSi2 covered with an ∼10nm CoxTiy(O)Siz surface layer. The epitaxial CoSi2 layer was thermally stable up to 1000°C, had a resistivity of ∼20μΩ-cm, and consumed ∼300Å of Si, thereby satisfying the most stringent deep submicron device contact scaling requirements.

Amorphous Phase Formation of Titanium Silicide on The 4° off-Axis and on-Axis Si(100) Substrates

1996 ◽  
Vol 427 ◽  
Author(s):  
Hyeongtag Jeon ◽  
Sukjae Lee ◽  
Hwackjoo Lee ◽  
Hyun Ruh
Keyword(s):  
Layer Thickness ◽  
Amorphous Layer ◽  
Film Deposition ◽  
Titanium Silicide ◽  
Atomic Scale ◽  
Phase Identification ◽  
Atomic Steps ◽  
Si Substrates ◽  
Annealing Temperatures ◽  
Scale Roughness

AbstractTwo different Si(100) substrates, the 4°off-axis and the on-axis Si(100), were prepared. Ti thin films were deposited in an e-beam evaporation system and the amorphous layers of Ti-silicide were formed at different annealing temperatures. The Si(100) substrates before Ti film deposition were examined with AFM to verify the atomic scale roughness of the initial Si substrates. The amorphous layer was observed by HRTEM and TEM. And the chemical analysis and phase identification were examined by AES and XRD. The Si(100) substrate after HF clean shows the atomic scale microroughness such as atomic steps and pits on the Si surface. The on-axis Si(100) substrate exhibits much rougher surface morphologies than those of the off-axis Si(100). These differences of atomic scale roughnesses of Si substrates result in the difference of the thicknesses of amorphous Ti-silicide layers. The amorphous layer thicknesses on the on-axis exhibit thicker than those of the off-axis Si(100) and these differences inamorphous layer thicknesses became decreased as annealing temperatures increased. These indicate that the role of the atomic scale roughness on the amorphous layer thickness is much significant at low temperatures. In this study, the correlation between the atomic scale roughness and the amorphous layer thickness is discussed in terms of the atomic steps and pits based on the observation with using analysis tools such as AFM, TEM and HRTEM.

Fabrication and Resistance-Switching Behaviors of NiO Thin Films by Thermal Oxidation of Evaporated Ni Films

2009 ◽  
Vol 66 ◽  
pp. 131-134
Author(s):  
X. Cao ◽  
Xiao Min Li ◽  
Wei Dong Yu ◽  
Rui Yang ◽  
Xin Jun Liu
Keyword(s):  
Thin Films ◽  
Thermal Oxidation ◽  
Resistive Switching ◽  
Resistance Switching ◽  
Si Substrates ◽  
Current Compliance

Polycrystalline NiO thin films were fabricated on Pt (111)/Ti/SiO2/Si substrates by thermal oxidation of the evaporated Ni films. Pt/NiO/Pt structures were prepared, and they showed reversible resistance switching behaviors. When the compliance set current was varied from 5 mA to 40 mA, the on-state currents increased, while the on-state resistances decreased. It is probably attributed to higher current compliance resulted in the formation of stronger and less resistive filaments, which in turn need more energy and power for their rupture. The resistive switching in NiO thin films is closely related to the formation and rupture of conducting filaments.

The Effect of Oxide Trenches on Defect Formation and Evolution in Ion-Implanted Silicon

2004 ◽  
Vol 810 ◽  
Author(s):  
Nina Burbure ◽  
Kevin S. Jones
Keyword(s):  
Silicon Oxide ◽  
Defect Formation ◽  
Solid Phase ◽  
Amorphous Layer ◽  
Oxide Interface ◽  
Cross Sectional ◽  
Patterned Wafers ◽  
Edge Defects ◽  
Formation And Evolution ◽  
Spike Anneal

ABSTRACTPattern induced defects during advanced CMOS processing can lead to lower quality devices with high leakage currents. Within this study, the effects of oxide trenches on implant related defect formation and evolution in silicon patterned wafers is examined. Oxide filled trenches approximately 4000Å deep were patterned into 300 mm <100> silicon wafers. Patterning was followed by ion implantation of Si+ at energies ranging from 10 to 80 keV. Samples were amorphized with doses of 1×1015 atoms/cm2, 5×1015 atoms/cm2, and 1×1016 atoms/cm2. Two independent repeating structures were studied. The first structure is comprised of silicon oxide filled trench lines, 3.7μm wide spaced 12.5μm apart, while the second structure contains silicon squares, 0.6μm on a side, surrounded by a silicon oxide filled trench. Cross- sectional and planar view transmission electron microscopy (TEM) samples were used to examine the defect morphology after annealing at temperatures ranging from 700°C to 950°C and at times between 1 second and 1 minute. Following complete regrowth, an array of defects was observed to form near the surface at the silicon/silicon oxide interface. These trench edge defects appeared to nucleate at the amorphous-crystalline interface for all energies and doses studied. Upon a spike anneal at 700°C, it was observed that regrowth of the amorphous layer had completed except in the region near the trench edge. Thus, it is believed that this defect results from the pinning of the amorphous-crystalline interface along the trench edge during solid phase epitaxial regrowth (SPER).

Integration of NiSi SALICIDE for Deep Submicron CMOS Technologies

1998 ◽  
Vol 514 ◽  
Author(s):  
X. W. Lin ◽  
N. Ibrahim ◽  
L. Topete ◽  
D. Pramanik
Keyword(s):  
Thin Films ◽  
Single Crystal ◽  
Sheet Resistance ◽  
Thermal Annealing ◽  
Cmos Technology ◽  
Deep Submicron ◽  
Thermal Budget ◽  
Si Substrates ◽  
Low Thermal Budget ◽  
Lower Resistivity

ABSTRACTA NiSi-based self-aligned silicidation (SALICIDE) process has been integrated into a 0.25 Ion CMOS technology. It involves rapid thermal annealing (RTA) of Ni thin films (300, Å thick) on Si substrates in the temperature range ≈400 - 700 °C. It was found that the NiSi sheet resistance (Rs) gradually decreases with decreasing linewidth. Parameters, such as RTA temperature, substrate dopant (As vs BF2) and structure (single crystal vs poly), were found to have little effects on Rs. NiSi forms a smoother interface with single crystalSi than with poly Si, and has a slightly lower resistivity. MOSFETs based on NiSi show comparable device characteristics to those obtained with Ti SALICIDE. Upon thermal annealing, NiSi remains stable at 450 °C for more than 39 hours. The same is true for 500 °C anneals up to 6 hours, except for NiSi narrow lines (<0.5 μm) on n+ poly Si substrates whose Rs is moderately increased after a 6 hr anneal. This work demonstrates that with an appropriate low-thermal budget backend process, NiSi SALICIDE can be a viable process for deep submicron ULSI technologies.

Variations of a Ni-P Surface Layer After Nanoparticle Impacts

2005 ◽  
Author(s):  
J. Xu ◽  
J. B. Luo ◽  
G. S. Pan ◽  
W. Zhang ◽  
X. C. Lu
Keyword(s):  
Surface Layer ◽  
Microscopic Examination ◽  
Wear Mechanisms ◽  
Erosive Wear ◽  
Experimental Results ◽  
Phosphorus Concentration ◽  
Fluid Medium ◽  
Abrasive Particles ◽  
Nano Scale ◽  
Surface Collision

In CMP, erosive wear regarded as one of the wear mechanisms underlying the interaction between the abrasive particles and polished surfaces can occur when materials are removed from surface collision of particles which are carried by a fluid medium. In this paper, the microscopic examination of the NiP coatings after nanoparticle impacts is performed. The experimental results indicate that craters and scratches can be observed in the surface after nanoparticle impacts, and crystal grains in nano-scale and element phosphorus concentration can be found in the sub-surface layer of the impacted surface.

Crystallization and electrical resistivity of Cu2O and CuO obtained by thermal oxidation of Cu thin films on SiO2/Si substrates

2012 ◽  
Vol 520 (20) ◽  
pp. 6368-6374 ◽  
Author(s):  
L. De Los Santos Valladares ◽  
D. Hurtado Salinas ◽  
A. Bustamante Dominguez ◽  
D. Acosta Najarro ◽  
S.I. Khondaker ◽  
...  
Keyword(s):  
Thin Films ◽  
Electrical Resistivity ◽  
Thermal Oxidation ◽  
Si Substrates

TEM Observations on the Evolution of Grain Structure in Pressurized Al-0.5Cu Thin Films

1998 ◽  
Vol 516 ◽  
Author(s):  
H.D. Yang ◽  
C.-U. Kim ◽  
M. Saran ◽  
H.A. Le
Keyword(s):  
Thin Films ◽  
Annealing Process ◽  
Grain Structure ◽  
Dislocation Slip ◽  
Grain Refining ◽  
Si Substrates ◽  
Primary Mechanism ◽  
Transmission Electron ◽  
Compressive Pressure ◽  
Ar Gas

AbstractThis paper reports the observations of the grain-refining mechanism found in Al-0.5Cu thin films that are subjected to hydrostatic compressive pressure during the annealing process. The films are deposited on Si substrates and subsequently placed under 60 MPa Ar gas pressure at 400°C. Transmission electron microscopy on these films reveals that plastic deformation occurs by dislocation slip and induces a refined grain structure. Polygonization is the primary mechanism for grain refining, resulting in the formation of sub-grain boundaries.

Nanocrystalline structure of surface layer of technical-purity titanium subjected to induction-thermal oxidation

2013 ◽  
Vol 39 (11) ◽  
pp. 969-971 ◽  
Author(s):  
A. A. Fomin ◽  
A. B. Steinhauer ◽  
I. V. Rodionov ◽  
M. A. Fomina ◽  
A. M. Zakharevich
Keyword(s):  
Surface Layer ◽  
Thermal Oxidation ◽  
Nanocrystalline Structure ◽  
Purity Titanium
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