A Dual-Function Uhv-Compatible Chamber for i) Low-Temperature Plasma-Assisted Oxidation, and ii) High-Temperature Rapid Thermal Processing of Si-Based Dielectric Gate Heterostructures

1993 ◽  
Vol 303 ◽  
Author(s):  
S. Hattangady ◽  
X-L Xu ◽  
M.J. Watkins ◽  
B. Hornung ◽  
V. Misra ◽  
...  

ABSTRACTA combination of i) low-temperature, 300-400°C, plasma-assisted oxidation to form the SiO2/Si interfaces, and ii) 800°C rapid thermal chemical vapor deposition, RTCVD, to deposit SiO2 thin films have been used to fabricate gate-oxide heterostructures. This sequence separates SiO2/Si interface formation by the oxidation process from the deposition of the bulk oxide layer by RTCVD. These two processes were performed in situ and sequentially in a single-chamber, ultraclean quartz reactor system. We have studied the chemistry of the interface formation process by Auger electron spectroscopy, AES, and the electrical properties of MOS devices with Al electrodes by C-V techniques.

1993 ◽  
Vol 300 ◽  
Author(s):  
S. Hattiangady ◽  
X-L Xu ◽  
M.J. Watkins ◽  
B. Hornung ◽  
V. Misra ◽  
...  

ABSTRACTA combination of i) low-temperature, 300-400°C, plasma-assisted oxidation to form the SiO2/Si interfaces, and ii) 800°C rapid thermal chemical vapor deposition, RTCVD, to deposit SiO2 thin films have been used to fabricate gate-oxide heterostructures. This sequence separates SiO2/Si interface formation by the oxidation process from the deposition of the bulk oxide layer by RTCVD. These two processes were performed in situ and sequentially in a single-chamber, ultraclean quartz reactor system. We have studied the chemistry of the interface formation process by Auger electron spectroscopy, AES, and the electrical properties of MOS devices with Al electrodes by C-V techniques.


2018 ◽  
Vol 2018 (1) ◽  
pp. 000728-000733
Author(s):  
Piotr Mackowiak ◽  
Rachid Abdallah ◽  
Martin Wilke ◽  
Jash Patel ◽  
Huma Ashraf ◽  
...  

Abstract In the present work we investigate the quality of low temperature Plasma Enhanced Chemical Vapor Deposition (PECVD) and plasma treated Tetraethyl orthosilicate (TEOS)-based TSV-liner films. Different designs of Trough Silicon Via (TSV) Test structures with 10μm and 20μm width and a depth of 100μm have been fabricated. Two differently doped silicon substrates have been used – highly p-doped and moderately doped. The results for break-through, resistivity and capacitance for the 20μm structures show a better performance compared to the 10μm structures. This is mainly due to increased liner thickness in the reduced aspect ratio case. Lower interface traps and oxide charge densities have been observed in the C-V measurements results for the 10μm structures.


2001 ◽  
Vol 40 (Part 1, No. 1) ◽  
pp. 44-48 ◽  
Author(s):  
Haiping Liu ◽  
Sughoan Jung ◽  
Yukihiro Fujimura ◽  
Chisato Fukai ◽  
Hajime Shirai ◽  
...  

Sign in / Sign up

Export Citation Format

Share Document