Alternative Materials for Micro-Electro-Mechanical Device Construction

1992 ◽  
Vol 276 ◽  
Author(s):  
R. H. Hackeit ◽  
L. E. Larson
Keyword(s):  
Plasma Etching ◽  
Silicon Oxide ◽  
Metal Films ◽  
Device Processing ◽  
Low Temperature Processing ◽  
Alternative Materials ◽  
Lift Off ◽  
Mechanical Devices ◽  
Silicon Based ◽  
Process Constraints

ABSTRACTIn order to integrate micro actuators with III-V semiconductor devices, we have devised Micro-Electro-Mechanical devices (MEM's), constructed from materials and processes common to existing III-V device processing. These processes are substantially different from silicon based processes because of the requirements for low temperature processing and the use of gold-based metallizations.Our material choices include, vacuum deposited and plated metal films, silicon oxide and nitride dielectric layers, and polyimide layers and structures. Sacrificial layers are implemented with photoresist rather than the more common silicon dioxide. The processes available are based on the ‘lift off’ of unwanted areas of the metal films, wet plating of metals through openings in photoresist masks, and wet and plasma etching of metals and dielectrics.This paper will discuss why we are using these materials, the process constraints imposed by the materials, the measurement of some of the material properties, and will relate some progress in applications.

Low Temperature Device Processing Technology for II-VI Semiconductors

1989 ◽  
Vol 161 ◽  
Author(s):  
D.L. Dreifus ◽  
R.M. Kolbas ◽  
B.P. Sneed ◽  
J.F. Schetzina
Keyword(s):  
Low Temperature ◽  
Field Effect ◽  
Field Effect Transistors ◽  
Epitaxial Layers ◽  
Processing Technologies ◽  
Device Processing ◽  
Device Structures ◽  
Lift Off ◽  
Processing Steps

ABSTRACTLow temperature (<60° C) processing technologies that avoid potentially damaging processing steps have been developed for devices fabricated from II-VI semiconductor epitaxial layers grown by photoassisted molecular beam epitaxy (MBE). These low temperature technologies include: 1) photolithography (1 µm geometries), 2) calibrated etchants (rates as low as 30 Å/s), 3) a metallization lift-off process employing a photoresist profiler, 4) an interlevel metal dielectric, and 5) an insulator technology for metal-insulator-semiconductor (MIS) structures. A number of first demonstration devices including field-effect transistors and p-n junctions have been fabricated from II-VI epitaxial layers grown by photoassisted MBE and processed using the technology described here. In this paper, two advanced device structures, processed at <60° C, will be presented: 1) CdTe:As-CdTe:In p-n junction detectors, grown in situ by photoassisted MBE, and 2) HgCdTe-HgTe-CdZnTe quantum-well modulation-doped field-effect transistors (MODFETs).

Surface Preparations Impact on 248nm Deep UV Photo Resists Adhesion during a Wet Etch

2012 ◽  
Vol 195 ◽  
pp. 58-61 ◽  
Author(s):  
Mathieu Foucaud ◽  
Philippe Garnier ◽  
Vincent Joseph ◽  
Erwine Pargon ◽  
Névine Rochat ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Plasma Etching ◽  
Integration Scheme ◽  
Metal Gate ◽  
Covalent Bonds ◽  
Gate Oxides ◽  
Process Step ◽  
High K ◽  
Lift Off ◽  
Wet Etch

Integrated circuits manufacturing still requires several wet etching operations in presence of photo resist. They are usually used to define the gate oxides or metal in a high k metal gate, gate first integration scheme. During this process step, the resist is used for masking and prevents the underneath material from being etched away. Wet treatments are preferred to plasma etching to perform this operation. Indeed, a smooth channels surface is mandatory to obtain a high carriers mobility. It is then critical to avoid any resist lift-off during the wet treatment in order to guarantee the underlying layers integrity. The observation of the lift-off phenomenon (figure 1) points out two possible root causes: 1) a lateral degradation of the covalent bonds at the interface between the polymer and the underlying material, and 2) a vertical resist degradation, due to the penetration of the etching chemicals into the resist down to the underlying material. Previous observations tend to link the lift-off severity to the bake temperature and the oxidation state of the surface on which the resist is coated.

scholarly journals Etch Processing of III-V Nitrides

1999 ◽  
Vol 4 (S1) ◽  
pp. 902-913 ◽  
Author(s):  
Charles R. Eddy
Keyword(s):  
Plasma Etching ◽  
Microwave Power ◽  
Ohmic Contacts ◽  
High Density ◽  
Etching Process ◽  
Ion Energy ◽  
Plasma Etching Process ◽  
Device Processing ◽  
The Impact ◽  
Density Plasma

As III-V nitride devices advance in technological importance, a fundamental understanding of device processing techniques becomes essential. Recent works have exposed various aspects of etch processes. The most recent advances and the greatest remaining challenges in the etching of GaN, AlN, and InN are reviewed. A more detailed presentation is given with respect to GaN high density plasma etching. In particular, the results of parametric and fundamental studies of GaN etching in a high density plasma are described. The effect of ion energy and mass on surface electronic properties is reported. Experimental results identify preferential sputtering as the leading cause of observed surface non-stoichiometry. This mechanism provides excellent surfaces for ohmic contacts to n-type GaN, but presents a major obstacle for Schottky contacts or ohmic contacts to p-type GaN. Chlorine-based discharges minimize this stoichiometry problem by improving the rate of gallium removal from the surface. In an effort to better understand the high density plasma etching process for GaN, in-situ mass spectrometry is employed to study the chlorine-based high density plasma etching process. Gallium chloride mass peaks were monitored in a highly surface sensitive geometry as a function of microwave power (ion flux), total pressure (neutral flux), and ion energy. Microwave power and pressure dependencies clearly demonstrate the importance of reactive ions in the etching of wide band gap materials. The ion energy dependence demonstrates the importance of adequate ion energy to promote a reasonable etch rate (≥100-150 eV). The benefits of ion-assisted chemical etching are diminished for ion energies in excess of 350 V, placing an upper limit to the useful ion energy range for etching GaN. The impact of these results on device processing will be discussed and future needs identified.

Influence of Gate Material and Process on Junctionless FET Subthreshold Performance

2016 ◽  
Vol 6 (2) ◽  
pp. 895
Author(s):  
Munawar A Riyadi ◽  
Irawan D Sukawati ◽  
Teguh Prakoso ◽  
Darjat Darjat
Keyword(s):  
Recent Progress ◽  
Electronic Device ◽  
Threshold Value ◽  
The Other ◽  
Subthreshold Slope ◽  
New Device ◽  
Nano Scale ◽  
Device Processing ◽  
Alternative Materials

The recent progress of dimension scaling of electronic device into nano scale has motivated the invention of alternative materials and structures. One new device that shows great potential to prolong the scaling is junctionless FET (JLFET). In contrast to conventional MOSFETs, JLFET does not require steep junction for source and drain. The device processing directly influence the performance, therefore it is crucial to understand the role of gate processing in JLFET. This paper investigates the influence of gate material and process on subthreshold performance of junctionless FET, by comparing four sets of gate properties and process techniques. The result shows that in terms of subthreshold slope, JLFET approaches near ideal value of 60 mV/decade, which is superior than the SOI FET for similar doping rate. On the other hand, the threshold value shows different tendencies between those types of device.

Fabrication of Silicon Based Fuel Cell Electrodes by Selective Plasma Etching

2019 ◽  
Vol 3 (1) ◽  
pp. 479-482
Author(s):  
Jose Geraldo A. Brito-Neto ◽  
Shintaro Araki ◽  
Soichi Shirako ◽  
Masanori Hayase
Keyword(s):  
Fuel Cell ◽  
Plasma Etching ◽  
Fuel Cell Electrodes ◽  
Silicon Based

MEMS Based One Shot Electro-Thermal Micro-Switches for System Reconfiguration

2006 ◽  
Author(s):  
Pierre Pennarun ◽  
Carole Rossi ◽  
Daniel Esteve ◽  
Denis Lagrange
Keyword(s):  
Plasma Etching ◽  
Energetic Material ◽  
Copper Electrodeposition ◽  
High Quality ◽  
System Reconfiguration ◽  
Long Time ◽  
Mems Technology ◽  
Lift Off ◽  
Electrical Connections ◽  
Spatial Redundancy

A new concept of one shot micro-switches is proposed. Different switches have been developed to achieve either ON-OFF switching or OFF-ON switching. They are based on electrothermal mechanisms. ON-OFF switching consists in breaking an electrical connection using energetic material or low melting point metal like aluminum. OFF-ON switching consists in micro-soldering locally two electrical connections. Switches commute with a few hundred of mW and do not need energy to stay in the stable OFF or ON state. These switches are particularly adapted to spatial redundancy applications that need high quality contact and reliable commutation even after long time storage. The fabrication process of these switches is based on classic MEMS technology steps (LPCVD, PECVD, copper electrodeposition, lift-off and plasma etching) and is IC compatible. Fabrication yield reaches 99%.

scholarly journals Interface Roughness Effects in Ultra-Thin Tunneling Oxides

VLSI Design ◽  
1998 ◽  
Vol 8 (1-4) ◽  
pp. 47-51 ◽  
Author(s):  
D. Z.-Y. Ting ◽  
Erik S. Daniel ◽  
T. C. Mcgill
Keyword(s):  
Silicon Oxide ◽  
Theoretical Study ◽  
Interface Roughness ◽  
Oxide Interface ◽  
Roughness Effects ◽  
Direct Tunneling ◽  
Silicon Based

Advanced MOSFET for ULSI and novel silicon-based devices require the use of ultrathin tunneling oxides where non-uniformity is often present. We report on our theoretical study of how tunneling properties of ultra-thin oxides are affected by roughness at the silicon/oxide interface. The effect of rough interfacial topography is accounted for by using the Planar Supercell Stack Method (PSSM) which can accurately and efficiently compute scattering properties of 3D supercell structures. Our results indicate that while interface roughness effects can be substantial in the direct tunneling regime, they are less important in the Fowler-Nordheim regime.

Localized Laser-Assisted Deposition of Silicon,Silicon Nitride and Silicon Dioxide

1987 ◽  
Vol 101 ◽  
Author(s):  
Geoffrey Auvert ◽  
Yves Pauleau ◽  
Didier Tonneau
Keyword(s):  
Growth Rate ◽  
Silicon Nitride ◽  
Silicon Dioxide ◽  
Silicon Oxide ◽  
Unsolved Problem ◽  
Experimental Conditions ◽  
Formation Kinetics ◽  
Silicon Based ◽  
Kinetics Of ◽  
Silicon Silicon

ABSTRACTThe localized laser-induced deposition of an insulator for silicon-based microelectronics seems to be an unsolved problem. In order to understand the limiting mechanism in the deposition, the formation kinetics of silicon, silicon oxide and silicon nitride using various laser wavelengths and gas mixtures have been studied Depending upon wavelength and laser-induced temperature, various chemical reactions are involved. In the presence of ammonia, the growth rate of silicon nitride dots was found to be lower than the corresponding silicon deposition rate, indicating that deposition starts with silane decomposition followed by nitridation of silicon. By evaluating the influence of the wavelengths, the existence of a photolytic aided reaction is detected in the presence of 2.4 eV photons. In the presence of oxygen molecules and under most experimental conditions, no deposition occurs. The formation of volatile intermediate compounds can explain the difficulty of locally depositing silicon dioxide.

Influence of Surface Composition of Silicon-Based Material on their Bioactivity

2012 ◽  
Vol 512-515 ◽  
pp. 1826-1829
Author(s):  
Ya Ran Niu ◽  
Xue Bin Zheng ◽  
You Tao Xie
Keyword(s):  
Silicon Wafer ◽  
Plasma Spraying ◽  
Photoelectron Spectroscopy ◽  
Silicon Oxide ◽  
Surface Composition ◽  
Control Sample ◽  
Atomic Ratio ◽  
Air Plasma ◽  
Vacuum Plasma Spraying ◽  
Silicon Based

Silicon coatings were prepared by vacuum plasma spraying (VPS) and air plasma spraying (APS) technologies. The samples were hydrothermally treated and then incubated in simulated body fluid (SBF) to evaluate their bioactivity and silicon wafer was used as control sample at the same time. The SBF test showed that a Ca-P layer was formed on the surface of silicon wafer and VPS-Si coating after immersion in SBF for certain time, indicating their improved bioactivity. Whereas no Ca-P layer was found on the surface of APS-Si coating. The results of X-ray photoelectron spectroscopy showed that the Si/O atomic ratio and chemical depth profiles of the silicon oxide films on the surface of silicon wafer, VPS-Si and APS-Si coatings were different. The results indicated that the bioactivity difference of silicon-based material resulted from the different composition of their surface. Hydrothermal treatment maybe a favorable method to improve the bioactivity of silicon-based material having silicon oxide of non-stoichiometric Si/O atomic ratio.

Selective Laser Annealing For Device Processing

1982 ◽  
Vol 13 ◽  
Author(s):  
I.D. Calder ◽  
A.A. Naem ◽  
H.H. Naguib
Keyword(s):  
Plasma Etching ◽  
Laser Annealing ◽  
Wet Etching ◽  
Laser Crystallization ◽  
Initial Value ◽  
Step Potential ◽  
Device Processing ◽  
Potential Applications ◽  
Polysilicon Films ◽  
Ar Coating

ABSTRACTSelective laser crystallization of undoped polysilicon films has been achieved through the use of a patterned Si3N4 anti-reflection (AR) coating. The recrystallized poly-Si beneath the AR cap exhibits an etch rate 50–90% lower than the surrounding uncapped material, allowing anisotropic etching of poly-Si for the fabrication of MOSFET gates. Undercut is reduced by at least a factor of two from unannealed material. Annealed edge profiles are uniform within ±0.03μm for plasma etching (±0.05 for wet etching) compared to ±0.1μm (± 0.25μm for wet etching) for unannealed regions. The sheet resistivity of 0.5μm films doped by phosphorus diffusion was reduced from an initial value of 82±5 Ω/□ to 40±8 Ω/□ when the dopant was diffused into recrystallized poly-Si and to a final value of 10.2 ± 0.2 Ω/□; after a further laser activation step. Potential applications in VLSIC processing are discussed.

Sign in / Sign up

Export Citation Format

Share Document