Transport Modeling and Compensation Mechanism for Semi-Insulating LT-Gaas and InP: Cu

1991 ◽  
Vol 241 ◽  
Author(s):  
K. Xie ◽  
C. R. Wie
Keyword(s):  
Impurity Scattering ◽  
Band Model ◽  
Compensation Mechanism ◽  
Mobility Data ◽  
Carrier Scattering ◽  
Deep Donor ◽  
Neutral Impurity ◽  
Major Carrier ◽  
Precipitate Model ◽  
Lt Gaas

ABSTRACTThe compensation mechanism and transport properties of annealed GaAs grown by molecular beam epitaxy at low substrate temperature (LT-GaAs) and Cu diffused InP are analyzed by using a deep donor band model and a precipitate model. It was found that the compensation in highly resistive LT GaAs can not be explained by the precipitate model alone, and therefore a high donor density had to be considered. In Cu diffused InP, the precipitate model gives a consistent explanation for the observed carrier compensation and mobility data. For both semi-insulating LT-GaAs and fully-compensated, lightly-doped InP:Cu, the neutral impurity scattering was found to be a major carrier scattering mechanism.

Characterization of Mbe GaAs Layers Grown at 200°C–300°C

1990 ◽  
Vol 198 ◽  
Author(s):  
C.R. Wie ◽  
K. Xie ◽  
T.T. Bardin ◽  
J.G. Pronko ◽  
D.C. Look ◽  
...  
Keyword(s):  
Activation Energy ◽  
Phonon Scattering ◽  
Impurity Scattering ◽  
Lattice Parameter ◽  
Annealed Sample ◽  
Polar Optical Phonon ◽  
Optical Phonon Scattering ◽  
Deep Donor ◽  
Neutral Impurity

ABSTRACTLattice parameter, RBS channeling, and T-dependent Hall effect and resistivity are measured in 5 μm GaAs layers MBE-grown at 200°C, 250°C and 305°C, and subsequently annealed. Perpendicular lattice parameter was increased by 0.15% for 200 °C, 0.10% for 250°C, and 0.05% for 305°C sample. No parallel mismatch was observed. In annealing up to 800°C, most recovery of lattice parameter occured at 350°C-450°C. For samples annealed at 500° C − 600°C, the conductivity activation energy was higher in the furnace annealed sample than in the RTA-annealed sample, indicating possible depth nonuniformity in furnace annealed sample. The 600°C RTA annealed sample indicated a donor activation energy of 0.61 eV. A 600°C furnace annealed sample indicated the deep donor concentration of 1.5×1018 cm−3. Maximum mobility in the 500–600°C annealed sample was 3000–3500 cm2/Vs, limited by the neutral impurity scattering and polar optical phonon scattering.

scholarly journals Neutral impurity scattering in semiconductors

1975 ◽  
Vol 11 (12) ◽  
pp. 5208-5210 ◽  
Author(s):  
T. C. McGill ◽  
R. Baron
Keyword(s):  
Impurity Scattering ◽  
Neutral Impurity

Neutral impurity scattering in semiconductors

1996 ◽  
Vol 18 (7) ◽  
pp. 885-888
Author(s):  
B. Alkan
Keyword(s):  
Impurity Scattering ◽  
Neutral Impurity

scholarly journals Avaliação do desempenho do transistor MOS sem junções configurado como Nanofio ou FINFET

2020 ◽  
Author(s):  
◽  
T. A. Ribeiro
Keyword(s):  
Three Dimensional ◽  
Impurity Scattering ◽  
Coulomb Effect ◽  
Electrical Characteristics ◽  
Nanowire Transistors ◽  
Carrier Scattering ◽  
Effective Mobility ◽  
Junctionless Transistors ◽  
Transistor Mos ◽  
Long Channel

This work studies how the different gate configurations of junctionless transistors affects their electrical characteristics. Measurements were made on experimental junctionless transistors varying the fin width as well asthree-dimensional numerical simulations, which were calibrated with the experimental results, using the models that best apply to the physics of the junctionless devices. With the three-dimensional simulations adjusted for the fin width, a study was made based on the fin height and its electrical characteristics. These transistors can be configured either as FinFETs or as nanowires depending on the height of the silicon fin. It was obtained that junctionless FinFETs (fin height larger than the fin width), have their best electrical characteristics for long channel devices with narrow fin width and fin height with values greater than 30 nm. For junctionless nanowire transistors (similar fin height and fin width), the best potential can be seen with the decrease in the length of the channel, with narrow width and short height of the silicon fin (around 10 nm). The mobility of the experimental devices analyzed by the Split-CV method, obtaining the effective mobility of the transistors. It was obtained that for a decrease in the fin width it increases the mobility, due to the reduction of Ionized Impurity scattering. Measurements were also made due to the high temperature in triple gate junctionless nanowire transistors to almost planar devices in the range of 300 K to 500 K. It was analyzed by the effective mobility, the effects of the types of carrier scattering depending on the fin width experimentally and via simulations. It has been seen that quasi-planar transistors suffer less from the scattering effect by phonons compared to nanowires, the latter having a greater influence of surface roughness. Comparing the temperature exponents, junctionless transistors suffer more from the effect of scattering by phonons than with Coulomb effect in transistors with narrow fin width. Thus, narrow fin width devices have a greater variation of mobility with temperature compared to quasi-planar devices

scholarly journals Avaliação do desempenho do transistor MOS sem junções configurado como Nanofio ou FINFET

2020 ◽  
Author(s):  
◽  
T. A. Ribeiro
Keyword(s):  
Three Dimensional ◽  
Impurity Scattering ◽  
Coulomb Effect ◽  
Electrical Characteristics ◽  
Nanowire Transistors ◽  
Carrier Scattering ◽  
Effective Mobility ◽  
Junctionless Transistors ◽  
Transistor Mos ◽  
Long Channel

This work studies how the different gate configurations of junctionless transistors affects their electrical characteristics. Measurements were made on experimental junctionless transistors varying the fin width as well asthree-dimensional numerical simulations, which were calibrated with the experimental results, using the models that best apply to the physics of the junctionless devices. With the three-dimensional simulations adjusted for the fin width, a study was made based on the fin height and its electrical characteristics. These transistors can be configured either as FinFETs or as nanowires depending on the height of the silicon fin. It was obtained that junctionless FinFETs (fin height larger than the fin width), have their best electrical characteristics for long channel devices with narrow fin width and fin height with values greater than 30 nm. For junctionless nanowire transistors (similar fin height and fin width), the best potential can be seen with the decrease in the length of the channel, with narrow width and short height of the silicon fin (around 10 nm). The mobility of the experimental devices analyzed by the Split-CV method, obtaining the effective mobility of the transistors. It was obtained that for a decrease in the fin width it increases the mobility, due to the reduction of Ionized Impurity scattering. Measurements were also made due to the high temperature in triple gate junctionless nanowire transistors to almost planar devices in the range of 300 K to 500 K. It was analyzed by the effective mobility, the effects of the types of carrier scattering depending on the fin width experimentally and via simulations. It has been seen that quasi-planar transistors suffer less from the scattering effect by phonons compared to nanowires, the latter having a greater influence of surface roughness. Comparing the temperature exponents, junctionless transistors suffer more from the effect of scattering by phonons than with Coulomb effect in transistors with narrow fin width. Thus, narrow fin width devices have a greater variation of mobility with temperature compared to quasi-planar devices

Characterization of Electrical Properties of Low Temperature GaAs

1991 ◽  
Vol 241 ◽  
Author(s):  
Bin Wu ◽  
Ashish Verma ◽  
John Gamelin ◽  
Hyunchul Sohn ◽  
Shyh Wang
Keyword(s):  
Computer Simulation ◽  
Steady State ◽  
High Frequency ◽  
Deep Donor ◽  
Shallow Acceptors ◽  
Cv Measurements ◽  
Low Temperature Gaas ◽  
Trap Filling ◽  
Lt Gaas

ABSTRACTLT GaAs(220°C) was grown on an n+ substrate and capped with n+ GaAs grown at 600°C (n-i-n). Complete IV and CV measurements were performed. The IV characteristics exhibit ohmic, trap-filling and space-charge-limited regimes. We have developed a model based upon the compensation of background shallow acceptors by deep donor traps, large concentrations of which have been shown to exist in LT GaAs. Computer simulation of the IV curve is compared with experimental results. The “breakdown” is attributed to trapfilling under electron injection. It is also found that when the voltage across the structure is changed, the current takes several seconds to reach steady state. This is consistent with our model, which assumes slow trapping and detrapping in the LT GaAs. High frequency CV measurements show the capacitance to be fairly constant for voltages below “breakdown”.

Indications of strong neutral impurity scattering in Ba(Sn,Sb)O3single crystals

2013 ◽  
Vol 88 (12) ◽  
Author(s):  
Hyung Joon Kim ◽  
Jiyeon Kim ◽  
Tai Hoon Kim ◽  
Woong-Jhae Lee ◽  
Byung-Gu Jeon ◽  
...  
Keyword(s):  
Impurity Scattering ◽  
Neutral Impurity

scholarly journals Manipulation of ionized impurity scattering for achieving high thermoelectric performance in n-type Mg3Sb2-based materials

2017 ◽  
Vol 114 (40) ◽  
pp. 10548-10553 ◽  
Author(s):  
Jun Mao ◽  
Jing Shuai ◽  
Shaowei Song ◽  
Yixuan Wu ◽  
Rebecca Dally ◽  
...  
Keyword(s):  
Power Factor ◽  
Carrier Mobility ◽  
Phonon Scattering ◽  
Impurity Scattering ◽  
Substantial Improvement ◽  
Thermoelectric Performance ◽  
Scattering Mechanism ◽  
Carrier Scattering ◽  
Ionized Impurity Scattering ◽  
Higher Carrier Mobility

Achieving higher carrier mobility plays a pivotal role for obtaining potentially high thermoelectric performance. In principle, the carrier mobility is governed by the band structure as well as by the carrier scattering mechanism. Here, we demonstrate that by manipulating the carrier scattering mechanism in n-type Mg3Sb2-based materials, a substantial improvement in carrier mobility, and hence the power factor, can be achieved. In this work, Fe, Co, Hf, and Ta are doped on the Mg site of Mg3.2Sb1.5Bi0.49Te0.01, where the ionized impurity scattering crosses over to mixed ionized impurity and acoustic phonon scattering. A significant improvement in Hall mobility from ∼16 to ∼81 cm2⋅V−1⋅s−1 is obtained, thus leading to a notably enhanced power factor of ∼13 μW⋅cm−1⋅K−2 from ∼5 μW⋅cm−1⋅K−2. A simultaneous reduction in thermal conductivity is also achieved. Collectively, a figure of merit (ZT) of ∼1.7 is obtained at 773 K in Mg3.1Co0.1Sb1.5Bi0.49Te0.01. The concept of manipulating the carrier scattering mechanism to improve the mobility should also be applicable to other material systems.

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