Measurement of Viscoelastic Stress Relief in Patterned Silicon-on-Insulator Composite Structures With Raman Spectroscopy

1991 ◽  
Vol 239 ◽  
Author(s):  
T. J. Létavic ◽  
E. W. Maby ◽  
R. J. Gutmann ◽  
J. Petruzzello
Keyword(s):  
Raman Spectroscopy ◽  
Plane Stress ◽  
Composite Structures ◽  
Silicon Layer ◽  
Stress Relief ◽  
High Temperature Stress ◽  
Fused Silica ◽  
Silicon On Insulator ◽  
Active Device ◽  
Measured Strain

ABSTRACTRaman spectroscopy has been utilized to measure room-temperature residual strain in the active device layer of laser-recrystallized silicon-on-insulator (SOI) composite structures. The SOI composite structures were fabricated on synthetic fused-silica substrates, and the composites contained a phosphosilicate glass (PSG) layer to provide high-temperature stress relief. Conventional masking and etching techniques were used to selectively pattern the polycrys-talline silicon layer into isolated square islands prior to recrystallization. The biaxial in-plane stress in recrystallized films was calculated from the measured strain-induced first-order Stokes Raman wavenumber shifts, and the results indicate that 200- μm-square recrystallized silicon islands have significantly lower in-plane stress values than continuous recrystallized silicon films. These measurements provide a preliminary confirmation of the dependence of the time constant for viscoelastic stress relief on the in-plane pattern dimension.

Non-Destructive Assessment of Thin Film Stresses and Crystal Qualify of Silicon on Insulator Materials with Raman Spectroscopy

1990 ◽  
Vol 188 ◽  
Author(s):  
Ingrid De Wolf ◽  
Jan Vanhellemont ◽  
Herman E. Maes
Keyword(s):  
Thin Film ◽  
Electron Microscopy ◽  
Raman Spectroscopy ◽  
Cross Section ◽  
Silicon Layer ◽  
Silicon On Insulator ◽  
Micro Raman Spectroscopy ◽  
Transmission Electron ◽  
Non Destructive ◽  
Zone Melt

ABSTRACTMicro Raman spectroscopy (RS) is used to study the crystalline quality and the stresses in the thin superficial silicon layer of Silicon-On-Insulator (SO) materials. Results are presented for SIMOX (Separation by IMplanted OXygen) and ZMR (Zone Melt Recrystallized) substrates. Both as implanted and annealed SIMOX structures are investigated. The results from the as implanted structures are correlated with spectroscopic ellipsometry (SE) and cross-section transmission electron microscopy (TEM) analyses on the same material. Residual stress in ZMR substrates is studied in low- and high temperature gradient regions.

Thin-Film Transistors in CO2-Laser Crystallized Silicon Films On Fused Silica

1982 ◽  
Vol 13 ◽  
Author(s):  
N. M. Johnson ◽  
H. C. Tuan ◽  
M. D. Moyer ◽  
M. J. Thompson ◽  
D. K. Biegelsen ◽  
...  
Keyword(s):  
Thin Film ◽  
Thin Film Transistors ◽  
Single Crystal Silicon ◽  
Silicon Layer ◽  
Fused Silica ◽  
Silicon Films ◽  
Silicon On Insulator ◽  
Bulk Glass ◽  
Crystal Silicon ◽  
Glass Substrates

ABSTRACTThin-film transistors (TFT) have been fabricated in scanned CO2 laser-crystallized silicon films on bulk fused silica. In n-channel enhancement-mode transistors, it is demonstrated that an excessively large leakage current can be electric-field modulated with a gate electrode located beneath the silicon layer. This dual-gate configuration provides direct verification on bulk glass substrates of back-channel leakage as has recently been demonstrated for beam-crystallized silicon films on thermal oxides over silicon wafers. With the application of deep-channel ion implantation to suppress back-channel leakage, high-peformance TFTs have been fabricated in single-crystal silicon films on fused silica. The results demonstrate that scanned CO 2 laser processing of silicon films on bulk glass can provide the basis for a silicon-on-insulator technology.

In Situ microscopy of the anodic etching of silicon

1995 ◽  
Vol 53 ◽  
pp. 232-233
Author(s):  
Frances M. Ross ◽  
Peter C. Searson
Keyword(s):  
Composite Structures ◽  
High Surface ◽  
High Surface Area ◽  
Chemical Properties ◽  
Selective Etching ◽  
Silicon On Insulator ◽  
Second Phase ◽  
Porous Layers ◽  
New Class ◽  
Porous Semiconductors

Porous semiconductors represent a relatively new class of materials formed by the selective etching of a single or polycrystalline substrate. Although porous silicon has received considerable attention due to its novel optical properties1, porous layers can be formed in other semiconductors such as GaAs and GaP. These materials are characterised by very high surface area and by electrical, optical and chemical properties that may differ considerably from bulk. The properties depend on the pore morphology, which can be controlled by adjusting the processing conditions and the dopant concentration. A number of novel structures can be fabricated using selective etching. For example, self-supporting membranes can be made by growing pores through a wafer, films with modulated pore structure can be fabricated by varying the applied potential during growth, composite structures can be prepared by depositing a second phase into the pores and silicon-on-insulator structures can be formed by oxidising a buried porous layer. In all these applications the ability to grow nanostructures controllably is critical.

Analysis of Silicon-On-Insulator Structures Formed By Oxygen Ion Implantation

1985 ◽  
Vol 43 ◽  
pp. 300-301
Author(s):  
N. Lewis ◽  
E. L. Hall ◽  
A. Mogro-Campero ◽  
R. P. Love
Keyword(s):  
Ion Implantation ◽  
Single Crystal ◽  
Single Crystal Silicon ◽  
Silicon Layer ◽  
Device Fabrication ◽  
Silicon On Insulator ◽  
High Dose ◽  
Crystal Silicon ◽  
Oxygen Ion ◽  
Oxygen Ion Implantation

The formation of buried oxide structures in single crystal silicon by high-dose oxygen ion implantation has received considerable attention recently for applications in advanced electronic device fabrication. This process is performed in a vacuum, and under the proper implantation conditions results in a silicon-on-insulator (SOI) structure with a top single crystal silicon layer on an amorphous silicon dioxide layer. The top Si layer has the same orientation as the silicon substrate. The quality of the outermost portion of the Si top layer is important in device fabrication since it either can be used directly to build devices, or epitaxial Si may be grown on this layer. Therefore, careful characterization of the results of the ion implantation process is essential.

Behavior of contact-silicided TFSOI gate structures

1994 ◽  
Vol 52 ◽  
pp. 860-861
Author(s):  
N. David Theodore ◽  
Juergen Foerstner ◽  
Peter Fejes
Keyword(s):  
Semiconductor Device ◽  
Series Resistance ◽  
Field Effect Transistors ◽  
Silicon Layer ◽  
Device Fabrication ◽  
Silicon On Insulator ◽  
Continuous Layer ◽  
Buried Oxide ◽  
Device Structures ◽  
Thin Silicon

As semiconductor device dimensions shrink and packing-densities rise, issues of parasitic capacitance and circuit speed become increasingly important. The use of thin-film silicon-on-insulator (TFSOI) substrates for device fabrication is being explored in order to increase switching speeds. One version of TFSOI being explored for device fabrication is SIMOX (Silicon-separation by Implanted OXygen).A buried oxide layer is created by highdose oxygen implantation into silicon wafers followed by annealing to cause coalescence of oxide regions into a continuous layer. A thin silicon layer remains above the buried oxide (~220 nm Si after additional thinning). Device structures can now be fabricated upon this thin silicon layer.Current fabrication of metal-oxidesemiconductor field-effect transistors (MOSFETs) requires formation of a polysilicon/oxide gate between source and drain regions. Contact to the source/drain and gate regions is typically made by use of TiSi2 layers followedby Al(Cu) metal lines. TiSi2 has a relatively low contact resistance and reduces the series resistance of both source/drain as well as gate regions

scholarly journals A Flexible PI/Si/SiO2 Piezoresistive Microcantilever for Trace-Level Detection of Aflatoxin B1

Sensors ◽  
2021 ◽  
Vol 21 (4) ◽  
pp. 1118
Author(s):  
Yuan Tian ◽  
Yi Liu ◽  
Yang Wang ◽  
Jia Xu ◽  
Xiaomei Yu
Keyword(s):  
Single Crystal ◽  
Aflatoxin B1 ◽  
Single Crystal Silicon ◽  
Silicon Layer ◽  
Wheatstone Bridge ◽  
Silicon On Insulator ◽  
Passivation Layer ◽  
Spring Constant ◽  
Trace Level ◽  
Crystal Silicon

In this paper, a polyimide (PI)/Si/SiO2-based piezoresistive microcantilever biosensor was developed to achieve a trace level detection for aflatoxin B1. To take advantage of both the high piezoresistance coefficient of single-crystal silicon and the small spring constant of PI, the flexible piezoresistive microcantilever was designed using the buried oxide (BOX) layer of a silicon-on-insulator (SOI) wafer as a bottom passivation layer, the topmost single-crystal silicon layer as a piezoresistor layer, and a thin PI film as a top passivation layer. To obtain higher sensitivity and output voltage stability, four identical piezoresistors, two of which were located in the substrate and two integrated in the microcantilevers, were composed of a quarter-bridge configuration wheatstone bridge. The fabricated PI/Si/SiO2 microcantilever showed good mechanical properties with a spring constant of 21.31 nN/μm and a deflection sensitivity of 3.54 × 10−7 nm−1. The microcantilever biosensor also showed a stable voltage output in the Phosphate Buffered Saline (PBS) buffer with a fluctuation less than 1 μV @ 3 V. By functionalizing anti-aflatoxin B1 on the sensing piezoresistive microcantilever with a biotin avidin system (BAS), a linear aflatoxin B1 detection concentration resulting from 1 ng/mL to 100 ng/mL was obtained, and the toxic molecule detection also showed good specificity. The experimental results indicate that the PI/Si/SiO2 flexible piezoresistive microcantilever biosensor has excellent abilities in trace-level and specific detections of aflatoxin B1 and other biomolecules.

LOW-NOISE SILICON-ON-INSULATOR HALL DEVICES

2004 ◽  
Vol 04 (02) ◽  
pp. L345-L354 ◽  
Author(s):  
Y. HADDAB ◽  
V. MOSSER ◽  
M. LYSOWEC ◽  
J. SUSKI ◽  
L. DEMEUS ◽  
...  
Keyword(s):  
Noise Level ◽  
Low Voltage ◽  
Silicon Layer ◽  
Electrical Current ◽  
Low Noise ◽  
Silicon On Insulator ◽  
Technological Parameters ◽  
Wide Range ◽  
Hall Sensors ◽  
Soi Technology

Hall sensors are used in a very wide range of applications. A very demanding one is electrical current measurement for metering purposes. In addition to high precision and stability, a sufficiently low noise level is required. Cost reduction through sensor integration with low-voltage/low-power electronics is also desirable. The purpose of this work is to investigate the possible use of SOI (Silicon On Insulator) technology for this integration. We have fabricated SOI Hall devices exploring the useful range of silicon layer thickness and doping level. We show that noise is influenced by the presence of LOCOS and p-n depletion zones near the edges of the active zones of the devices. A proper choice of SOI technological parameters and process flow leads to up to 18 dB reduction in Hall sensor noise level. This result can be extended to many categories of devices fabricated using SOI technology.

Enhancement of Breakdown Voltage in SOI MOSFET Using Buried p-Type Silicon

2021 ◽  
Author(s):  
Deivakani M ◽  
Sumithra M.G ◽  
Anitha P ◽  
Jenopaul P ◽  
Priyesh P. Gandhi ◽  
...  
Keyword(s):  
Breakdown Voltage ◽  
Impact Ionization ◽  
Semiconductor Industry ◽  
Silicon Layer ◽  
Silicon On Insulator ◽  
Physical Models ◽  
Oxide Semiconductor ◽  
Soi Mosfet ◽  
P Type ◽  
Conventional Device

Abstract Semiconductor industry is still looking for the enhancement of breakdown voltage in Silicon on Insulator (SOI) Metal Oxide Semiconductor Field Effect Transistor (MOSFET). Thus, in this paper, heavy n-type doping below the channel is proposed for SOI MOSFET. Simulation of SOI MOSFET is carried out using 2D TCAD physical simulator. In the conventional device, with no p-type doping is used at the bottom silicon layer. While, in proposed device, p-type doping of 1×1018 cm-3 is used. Physical models are used in the simulation to achieve realistic performance. The models are mobility model, impact ionization model and ohmic contact model. Using TCAD simulation, electron/hole current density, impact generation, recombination and breakdown phenomena are analyzed. It is found that the proposed with p-type doping of 1×1018 cm-3 for SOI MOSFET yields high breakdown voltage. In contrast to conventional device, 20% improvement in breakdown voltage is achieved for proposed device.

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