Secondary Grain Growth in Heavily Doped Polysilicon During Rapid Thermal Annealing

1991 ◽  
Vol 230 ◽  
Author(s):  
S. Batra ◽  
K. Park ◽  
M. Lobo ◽  
S. Banerjee
Keyword(s):  
Grain Size ◽  
Film Thickness ◽  
Grain Growth ◽  
Thermal Annealing ◽  
Rapid Thermal Annealing ◽  
Silicon On Insulator ◽  
Active Devices ◽  
Drastic Increase ◽  
Heavily Doped ◽  
Soi Technology

AbstractTo successfully implement Silicon-on-Insulator (SOI) technology using polysilicon-on-oxide, it is necessary to maximize the grain size such that the active devices are entirely within very large single crystal grains. A drastic increase in grain size in polysilicon has been reported due to secondary grain growth in ultra-thin, heavily n-type doped films upon regular furnace annealing. Very little work has been undertaken, however, to study secondary grain growth during Rapid Thermal Annealing (RTA).This paper is a study of the grain growth mechanism in heavily P-doped, amorphous silicon films during RTA. Secondary grains as large as 16 μm have been obtained in 160 nm thick films after a 180 s RTA at 1200 °C, representing a grainsize- to-film-thickness-ratio of 100:1. This is the largest secondary grain size and grain-size-to-film-thickness reported in the literature. A detailed analysis of negatively charged silicon vacancies has also been employed to explain the lower activation energy (1.55 eV) of secondary grain growth compared to that of normal grain growth (2.4 eV).

Secondary Grain Growth During Rapid Thermal Annealing of Doped Polysilicon Films

1987 ◽  
Vol 92 ◽  
Author(s):  
R. C. Cammarata ◽  
C. V. Thompson ◽  
S. M. Garrison
Keyword(s):  
Grain Growth ◽  
Thermal Annealing ◽  
Rapid Thermal Annealing ◽  
Solid Phase ◽  
Silicon Substrates ◽  
Solid Phase Epitaxy ◽  
Polysilicon Films ◽  
Heavily Doped ◽  
Grain Growth Behavior ◽  
Short Times

ABSTRACTRecently there has been a great deal of interest in the use of thin (≤0.1µm) heavily doped polysilicon films as diffusion sources for shallow junctions in silicon substrates. It has been reported that grain growth and solid phase epitaxy occur during annealing of such films and that the apparent rates of both are much greater during rapid thermal annealing. We report similar grain growth behavior for rapid thermal annealed thin polysilicon films deposited onto amorphous SiO2. Based on these experimental results we propose that solid phase homoepitaxy in polysilicon films occurs via secondary grain growth. This process proceeds rapidly at first but slows down due to grain boundary drag. Rapid thermal annealing of polysilicon films provides a method for selectively utilizing the kinetic process that dominates for short times.

STRUCTURAL CHARACTERISTICS OF (Ba,Sr)TiO3 THIN FILMS BY RAPID THERMAL ANNEALING

2007 ◽  
Vol 14 (01) ◽  
pp. 141-145
Author(s):  
Q. Y. ZHANG ◽  
S. W. JIANG ◽  
Y. R. LI
Keyword(s):  
Thin Films ◽  
Grain Size ◽  
Heating Rate ◽  
Thermal Annealing ◽  
Rapid Thermal Annealing ◽  
Rapid Heating ◽  
Structural Characteristics ◽  
High Heating Rate ◽  
Duration Time ◽  
Temperature Heating

The rapid thermal annealing (RTA) process was adapted to crystallize the amorphous ( Ba,Sr ) TiO 3 thin films prepared on Si (111) substrates by RF magnetic sputtering deposition. The effect of annealing temperature, heating rate and duration time on crystallization was studied through X-ray diffraction and atomic force microscopy. The result shows that the crystallinity and grain size were strongly dependent on the temperature, heating rate, and duration time. Higher heating rate leads to smaller grain size. In high heating rate, the grain size shows different dependence of temperature from that of low heating rate. For a heating rate of 50°C/s, the grain size decreased with temperature increasing below 700°C, while after that temperature, the grain size increased slightly with the temperature increasing. At a certain temperature, the crystallinity and surface roughness improved with increase in annealing time, while grain size changed little. The effect of rapid heating rate on the nucleation and grain growth has been discussed, which contributes to the limited grain size of the annealed ( Ba,Sr ) TiO 3 thin films.

Formation and Morphology Evolution of Nickel Germanides on Ge (100) under Rapid Thermal Annealing

2004 ◽  
Vol 810 ◽  
Author(s):  
K.Y. Lee ◽  
S.L. Liew ◽  
S.J. Chua ◽  
D.Z. Chi ◽  
H.P. Sun ◽  
...  
Keyword(s):  
Grain Growth ◽  
Sheet Resistance ◽  
Thermal Annealing ◽  
Rapid Thermal Annealing ◽  
Microstructure Evolution ◽  
Interfacial Microstructure ◽  
Morphology Evolution ◽  
Smooth Interface ◽  
Substrate Side ◽  
Nickel Germanides

ABSTRACTPhase formation and interfacial microstructure evolution of nickel germanides formed by rapid thermal annealing in a 15-nm Ni/Ge (100) system have been studied. Coexistence of a NiGe layer and Ni-rich germanide particles was detected at 250°C. Highly textured NiGe film with a smooth interface with Ge was observed. Annealing at higher temperatures resulted in grain growth and severe grooving of the NiGe film at the substrate side, followed by serious agglomeration above 500°C. Fairly low sheet resistance was achieved in 250-500°C where the NiGe film continuity was uninterrupted.

Electroplated Cu Recrystallization in Damascene Structures at Elevated Temperatures

1999 ◽  
Vol 564 ◽  
Author(s):  
Qing-Tang Jiang ◽  
Michael E. Thomas ◽  
Gennadi Bersuker ◽  
Brendan Foran ◽  
Robert Mikkola ◽  
...  
Keyword(s):  
Crystal Structure ◽  
Grain Size ◽  
Film Thickness ◽  
Grain Growth ◽  
Elevated Temperatures ◽  
Retardation Effect ◽  
Cu Films ◽  
Grain Sizes ◽  
Geometrical Constraints ◽  
The Difference

AbstractTransformations in electroplated Cu films from a fine to course grain crystal structure (average grain sizes went from ∼0.1 µm to several microns) were observed to strongly depend on film thickness and geometry. Thinner films underwent much slower transformations than thicker ones. A model is proposed which explains the difference in transformation rates in terms of the physical constraint experienced by the film since grain growth in thinner films is limited by film thickness. Geometrical constraints imposed by trench and via structures appear to have an even greater retardation effect on the grain growth. Experimental observations indicate that it takes much longer for Cu in damascene structures to go through grain size transformations than blanket films.

Polysilicon Grain Growth by Rapid Isothermal Annealing

1984 ◽  
Vol 33 ◽  
Author(s):  
R. F. Pinizzotto ◽  
F. Y. Clark ◽  
S. D. S. Malhi ◽  
R. R. Shah
Keyword(s):  
Grain Size ◽  
Integrated Circuits ◽  
Film Thickness ◽  
Grain Growth ◽  
Isothermal Annealing ◽  
Three Dimensional ◽  
Oxide Thickness ◽  
Kinetics Of ◽  
Microstructure Of The Material ◽  
Short Times

ABSTRACTone method of reducing the area occupied by a RAM cell is to stack the p- and n-channel devices on top of one another. This “stacked CMOS” structure is a first step towards three dimensional integration. The simplest approach is to use polysilicon as the substrate for the top transistors. This paper describes the results of grain growth studies of samples annealed by rapid isothermal annealing. The temperature varied from 1100 to 1400°C and the anneal time varied from 10 to 480 seconds. TEM was used to examine the microstructure of the material. The grain growth was found to be film thickness limited, i.e. the final grain size was approximately the same as the initial film thickness. As a result, the kinetics of grain growth cannot be described by a simple logarithmic time law. There also is a velocity dependent drag contribution to the growth kinetics that implies impurities play an important role. The interlevel oxide thickness affects grain growth. Thicker oxides lead to faster growth, probably by reducing the heat flow to the silicon substrate. A capping layer was found to have no effect on the grain size. The above results indicate that it is possible to obtain large grains in short times using isothermal annealing. This process may be useful for fabricating stacked polysilicon layers in three-dimensional integrated circuits.

Stability of Ruthenium-Silica Bilayer Structures

1994 ◽  
Vol 343 ◽  
Author(s):  
Zara Weng-Sieh ◽  
Tai. D. Nguyen ◽  
Ronald Gronsky
Keyword(s):  
Grain Size ◽  
Film Thickness ◽  
Silicon Dioxide ◽  
Grain Growth ◽  
Original Film ◽  
Grain Sizes ◽  
Transmission Electron ◽  
20 Nm ◽  
Spherical Grains ◽  
Deposited Films

ABSTRACTThe microstructural evolution of ruthenium-silicon dioxide bilayer structures upon annealing is studied using transmission electron microscopy. SiO2/Ru/SiO2 structures, with thicknesses of 2/1/2 nm, 4/2/4 nm, 8/4/8 nm, and 20/10/20 nm, are formed by magnetron sputtering and annealed at 300 or 600°C. As-deposited films have grain sizes on the order of the Ru film thickness. After annealing at 600°C, significant grain growth is observed for all thicknesses, such that the final grain sizes are approximately 3 to 20x greater than the original film thickness. The largest increase in the average Ru grain size is observed for the 2 nm thick ruthenium film possibly due to the coalescence of Ru grains. The coalescence of the Ru particles in the 1 and 2 nm thick films results in the formation of lamellar Ru grains, which disrupts the contiguity of the Ru film. In all other cases, the increase in grain size is attributed to normal grain growth, but the formation of anomalous spherical grains is also observed.

Diffusion of Atoms Implanted in Poly Silicon Layer on Insulator

1987 ◽  
Vol 106 ◽  
Author(s):  
M. Takai ◽  
M. Izumi ◽  
T. Yamamoto ◽  
A. Kinomura ◽  
K. Gamo ◽  
...  
Keyword(s):  
Hall Effect ◽  
Thermal Annealing ◽  
Rapid Thermal Annealing ◽  
Silicon Layer ◽  
Silicon On Insulator ◽  
Tail Region ◽  
Furnace Annealing ◽  
Peak Region ◽  
Poly Silicon ◽  
Hall Effect Measurements

ABSTRACTDiffusion of arsenic implanted in poly-silicon on insulator structures after furnace and rapid thermal annealing (RTA) has been investigated by Rutherford backscattering (RBS) and Hall effect measurements. The diffusivity for As in poly–Si on insulator is represented by D = 3.12 × 104 exp (− 3.86/kT) cm/sec for the tail region after both RTA and furnace annealing and D = 34.0 exp (− 3.42/kT) cm2/sec for the peak region after RTA. Poly–Si layers after implantation and annealing were found to have tensile stresses of 3.0 – 4.0 kbar.

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