Si/Si1−xGex p-Channel Mosfets Fabricated Using a Gate Quality Dielectric Process

1991 ◽  
Vol 220 ◽  
Author(s):  
V. P. Kesan ◽  
S. Subbanna ◽  
M. J. Tejwani ◽  
P. J. Restle ◽  
S. S. Iyer
Keyword(s):  
Low Temperature ◽  
Interface State ◽  
State Density ◽  
Channel Structure ◽  
Direct Oxidation ◽  
High Quality ◽  
Gate Oxides ◽  
Si Substrates ◽  
Dual Channel ◽  
High Transconductance

ABSTRACTThe use of Si1−xGex alloys for p-channel high transconductance MOSFETs requires a high quality dielectric system. Direct oxidation of Si1−xGex alloys or even low temperature deposition of SiO2 directly on Si1−xGex results in a very high interface state density. We show that low interface state densities (below 1011 eV−1cm−2) can be obtained using both thermal and PECVD oxides through the use of a thin (6–8 nm) Si cap between the oxide and the Si1-xGex layer. The Si cap layer leads to a sequential turn-on of the Si1−xGex channel and the Si cap channel, as clearly observed in low temperature C-V curves. We show that this dual channel structure can be designed to suppress the parasitic Si cap channel. High quality, fully isolated Si1−xGex p-channel MOSFETs have been fabricated in an integrable, low Dt process using both thermal or PECVD gate oxides and selective UHV/CVD for the Si/ Si1−xGex channels. We show that optimally designed Si/Si1−xGex MOSFETs exhibit up to 70% higher transconductance at 300K than control Si devices fabricated on n-doped 1017/cm3 Si substrates. Si/Si1−xGex p-channel MOSFETs with thermal and PECVD gate oxides show comparable device characteristics.

scholarly journals Investigate on the Mechanism of HfO2/Si0.7Ge0.3 Interface Passivation Based on Low-Temperature Ozone Oxidation and Si-Cap Methods

Nanomaterials ◽  
2021 ◽  
Vol 11 (4) ◽  
pp. 955
Author(s):  
Qide Yao ◽  
Xueli Ma ◽  
Hanxiang Wang ◽  
Yanrong Wang ◽  
Guilei Wang ◽  
...  
Keyword(s):  
Low Temperature ◽  
Photoelectron Spectroscopy ◽  
Interface State ◽  
State Density ◽  
Oxide Semiconductor ◽  
Direct Oxidation ◽  
Ozone Oxidation ◽  
X Ray ◽  
Interface Passivation ◽  
Metal Oxide Semiconductor Capacitor

The interface passivation of the HfO2/Si0.7Ge0.3 stack is systematically investigated based on low-temperature ozone oxidation and Si-cap methods. Compared with the Al2O3/Si0.7Ge0.3 stack, the dispersive feature and interface state density (Dit) of the HfO2/Si0.7Ge0.3 stack MOS (Metal-Oxide-Semiconductor) capacitor under ozone direct oxidation (pre-O sample) increases obviously. This is because the tiny amounts of GeOx in the formed interlayer (IL) oxide layer are more likely to diffuse into HfO2 and cause the HfO2/Si0.7Ge0.3 interface to deteriorate. Moreover, a post-HfO2-deposition (post-O) ozone indirect oxidation is proposed for the HfO2/Si0.7Ge0.3 stack; it is found that compared with pre-O sample, the Dit of the post-O sample decreases by about 50% due to less GeOx available in the IL layer. This is because the amount of oxygen atoms reaching the interface of HfO2/Si0.7Ge0.3 decreases and the thickness of IL in the post-O sample also decreases. To further reduce the Dit of the HfO2/Si0.7Ge0.3 interface, a Si-cap passivation with the optimal thickness of 1 nm is developed and an excellent HfO2/Si0.7Ge0.3 interface with Dit of 1.53 × 1011 eV−1cm−2 @ E−Ev = 0.36 eV is attained. After detailed analysis of the chemical structure of the HfO2/IL/Si-cap/Si0.7Ge0.3 using X-ray photoelectron spectroscopy (XPS), it is confirmed that the excellent HfO2/Si0.7Ge0.3 interface is realized by preventing the formation of Hf-silicate/Hf-germanate and Si oxide originating from the reaction between HfO2 and Si0.7Ge0.3 substrate.

scholarly journals Demonstration of AlGaN/GaN MISHEMT on Si with Low-Temperature Epitaxy Grown AlN Dielectric Gate

Electronics ◽  
2020 ◽  
Vol 9 (11) ◽  
pp. 1858
Author(s):  
Matthew Whiteside ◽  
Subramaniam Arulkumaran ◽  
Yilmaz Dikme ◽  
Abhinay Sandupatla ◽  
Geok Ing Ng
Keyword(s):  
Low Temperature ◽  
Gate Dielectric ◽  
Drain Current ◽  
High Electron Mobility Transistors ◽  
Interface State ◽  
State Density ◽  
High Electron ◽  
Gate Leakage ◽  
Annealing Effects ◽  
Low Temperature Epitaxy

AlGaN/GaN metal-insulator-semiconductor high-electron-mobility transistors (MISHEMT) with a low-temperature epitaxy (LTE)-grown single crystalline AlN gate dielectric were demonstrated for the first time and the post-gate annealing effects at 400 °C were studied. The as-deposited LTE-AlN MISHEMT showed a maximum drain current (IDmax) of 708 mA/mm at a gate bias of 4 V and a maximum extrinsic transconductance (gmmax) of 129 mS/mm. The 400 °C annealed MISHEMT exhibited an increase of 15% in gmmax, an order of magnitude reduction in reverse gate leakage and about a 3% suppression of drain current (ID) collapse. The increase of gmmax by post-gate annealing is consistent with the increase of 2DEG mobility. The suppression of ID collapse and the reduction of gate leakage current is attributed to the reduction of interface state density (5.0 × 1011 cm−2eV−1) between the AlN/GaN interface after post-gate annealing at 400 °C. This study demonstrates that LTE grown AlN is a promising alternate material as gate dielectric for GaN-based MISHEMT application.

Low-temperature fabrication of high-quality (Ba, Sr)TiO3 films using charged liquid cluster beam method

2002 ◽  
Vol 17 (8) ◽  
pp. 1888-1891 ◽  
Author(s):  
Hyungsoo Choi ◽  
Sungho Park ◽  
Yi Yang ◽  
HoChul Kang ◽  
Kyekyoon (Kevin) Kim ◽  
...  
Keyword(s):  
Dielectric Constant ◽  
Low Temperature ◽  
Cluster Beam ◽  
High Quality ◽  
Carboxylate Ligands ◽  
Si Substrates ◽  
Beam Method ◽  
Temperature Deposition ◽  
Bst Films ◽  
Substrate Temperatures

Low-temperature deposition of high-quality (Ba, Sr)TiO3 (BST) thin films was achieved in air on Pt/Ti/SiO2/Si substrates using the charged liquid cluster beam (CLCB) method. The Ba, Sr, and Ti precursors were synthesized using alkoxy carboxylate ligands to tailor their physical properties to the CLCB process. The as-deposited BST films fabricated at substrate temperatures as low as 280 °C exhibited high purity. The leakage current density and dielectric constant of the film, deposited at 300 °C and subsequently annealed at 700 °C, were 2.5 × 10−9 A/cm2 at 1.5 V and 305, respectively.

Characterizations of Ultra-thin Dielectrics Grown by Microwave Afterglow O2/N2O Plasma Oxidation at Low Temperature with Rapid Thermal Annealing

1995 ◽  
Vol 387 ◽  
Author(s):  
Po-ching Chen ◽  
Klaus Yung-jane Hsu ◽  
Joseph J. Loferski ◽  
Huey-liang Hwang
Keyword(s):  
Low Temperature ◽  
Thermal Annealing ◽  
Rapid Thermal Annealing ◽  
Photoelectron Spectroscopy ◽  
Interface State ◽  
State Density ◽  
Interface State Density ◽  
Plasma Oxidation ◽  
X Ray ◽  
Thin Dielectrics

AbstractMicrowave afterglow plasma oxidation at a low temperature (600 °C ) and rapid thermal annealing (RTA) were combined to grow high quality ultra-thin dielectrics. This new approach has a low thermal budget. The mid-gap interface state density of oxides pretreated in N2O plasma was decreased to about 5×1010 cm−2eV−1 after rapid thermal annealing at 950 °C.It was found that RTA is very effective for relieving the oxide stress and reducing the interface state density. Nitrogen incorporated in oxides by the N2O plasma pretreatment of the Si surface helped to reduce the interface state density. Microstructures of ultra-thin oxide grown by microwave afterglow oxidation with or without RTA were revealed by extended-X-ray-absorption-finestructure (EXAFS) and X-ray photoelectron spectroscopy (XPS) analysis.

Analysis of Interface Trap Density and Channel Mobility in 4H-SiC NMOS Capacitors and Lateral MOSFETs

2017 ◽  
Vol 897 ◽  
pp. 115-118
Author(s):  
Martin Domeij ◽  
Jimmy Franchi ◽  
Krister Gumaelius ◽  
K. Lee ◽  
Fredrik Allerstam
Keyword(s):  
Threshold Voltage ◽  
Interface State ◽  
State Density ◽  
Interface State Density ◽  
Trap Density ◽  
Interface Trap Density ◽  
Interface Trap ◽  
Subthreshold Slope ◽  
Gate Oxides ◽  
Channel Mobility

Lateral implanted SiC MOSFETs and NMOS capacitors were fabricated and used to extract channel mobility and interface state density DIT for three different gate oxides. DIT values were extracted using the high(1 MHz)-low(1 kHz) method for NMOS capacitors and the subthreshold slope for MOSFETs. The subthreshold slope extraction gave 6-20 times higher DIT values compared to the high-low method, presumably because the high-low method cannot capture the fastest traps [1]. None of the methods resulted in clear proportionality between the inverse channel mobility and DIT. The subthreshold slope gave similar DIT values for samples with different surface p-doping concentrations indicating that the method is not sensitive to the threshold voltage.

Improved Dielectric and Interface Properties of 4H-SiC MOS Structures Processed by Oxide Deposition and N2O Annealing

2006 ◽  
Vol 527-529 ◽  
pp. 987-990 ◽  
Author(s):  
Tsunenobu Kimoto ◽  
H. Kawano ◽  
Masato Noborio ◽  
Jun Suda ◽  
Hiroyuki Matsunami
Keyword(s):  
Breakdown Strength ◽  
Oxide Thickness ◽  
Interface State ◽  
State Density ◽  
Interface Properties ◽  
Gate Oxides ◽  
Channel Mobility ◽  
Oxide Deposition ◽  
Mos Structures

Oxide deposition followed by high-temperature annealing in N2O has been investigated to improve the quality of 4H-SiC MOS structures. Annealing of deposited oxides in N2O at 1300oC significantly enhances the breakdown strength and decreases the interface state density to 3x1011 cm-2eV-1 at EC – 0.2 eV. As a result, high channel mobility of 34 cm2/Vs and 52 cm2/Vs has been attained for inversion-type MOSFETs fabricated on 4H-SiC(0001)Si and (000-1)C faces, respectively. The channel mobility shows a maximum when the increase of oxide thickness during N2O annealing is approximately 5 nm. A lateral RESURF MOSFET with gate oxides formed by the proposed process has blocked 1450 V and showed a low on-resistance of 75 mcm2, which is one of the best performances among lateral SiC MOSFETs reported.

Defect Control in Growth and Processing of 4H-SiC for Power Device Applications

2010 ◽  
Vol 645-648 ◽  
pp. 645-650 ◽  
Author(s):  
Tsunenobu Kimoto ◽  
Gan Feng ◽  
Toru Hiyoshi ◽  
Koutarou Kawahara ◽  
Masato Noborio ◽  
...  
Keyword(s):  
Interface State ◽  
State Density ◽  
Deep Levels ◽  
Extended Defects ◽  
Gate Oxides ◽  
Channel Mobility ◽  
Device Processing ◽  
Defect Control ◽  
Device Applications ◽  
Almost All

Extended defects and deep levels generated during epitaxial growth of 4H-SiC and device processing have been reviewed. Three types in-grown stacking faults, (6,2), (5,3), and (4,4) structures, have been identified in epilayers with a density of 1-10 cm-2. Almost all the major deep levels present in as-grown epilayers have been eliminated (< 1x1011 cm-3) by two-step annealing, thermal oxidation at 1150-1300oC followed by Ar annealing at 1550oC. The proposed two-step annealing is also effective in reducing various deep levels generated by ion implantation and dry etching. The interface properties and MOSFET characteristics with several gate oxides are presented. By utilizing the deposited SiO2 annealed in N2O at 1300oC, a lowest interface state density and a reasonably high channel mobility for both n- and p-channel MOSFETs with an improved oxide reliability have been attained.

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