The Deposition of Borophosphosilicate Glass Films by LPCVD Using 2,4,6,8 Tetramethylcyclotetrasiloxane

1990 ◽  
Vol 204 ◽  
Author(s):  
David L. O'Meara ◽  
Arthur K. Hochberg
Keyword(s):  
Integrated Circuit ◽  
Silicon Oxide ◽  
Chemical System ◽  
Safe Alternative ◽  
Liquid Source ◽  
Borophosphosilicate Glass ◽  
Reduced Pressures ◽  
Glass Films ◽  
Integrated Circuit Processing

ABSTRACTBorophosphosilicate glass (BPSG) films used in integrated circuit processing are grown from combinations of toxic and pyrophoric silane, diborane, and phosphine at atmospheric and reduced pressures. A safe, alternative chemical system has been developed with liquid source replacements for each dangerous gas. 2,4,6,8 tetramethylcyclotetrasiloxane (TMCTS) and oxygen are used as the silicon oxide sources, and trimethylphosphite (TMP) and trimethylborate (TMB) are the phosphorous and boron sources, respectively. Films grown in a hot wall LPCVD reactor with standard diffusion boats have thickness uniformities of ± 2 % and doping uniformities < ± 5 %.

Scanning Electron Microscope Induced Electrical Breakdown of Tungsten Windows in Integrated Circuit Processing

2004 ◽  
Author(s):  
David M. Shuttleworth ◽  
Mary Drummond Roby
Keyword(s):  
Electron Microscope ◽  
Scanning Electron Microscope ◽  
Contact Resistance ◽  
Integrated Circuit ◽  
Electrical Breakdown ◽  
Scanning Electron ◽  
Integrated Circuit Processing

Abstract Interaction of inline SEM inspections with tungsten window-1 integrity were investigated. Multiple SEMs were utilized and various points in the processing were inspected. It was found that in certain circumstances inline SEM inspection induced increased window-1 contact resistance in both source/drain and gate contacts, up to and including electrical opens for the source/drain contacts.

scholarly journals Modeling the Piezoelectric Cantilever Resonator with Different Width Layers

Sensors ◽  
2020 ◽  
Vol 21 (1) ◽  
pp. 87
Author(s):  
Zhenxi Liu ◽  
Jiamin Chen ◽  
Xudong Zou
Keyword(s):  
Resonance Frequency ◽  
Integrated Circuit ◽  
Silicon Oxide ◽  
Fem Simulation ◽  
Control Process ◽  
Design Tool ◽  
Piezoelectric Cantilever ◽  
Simulation And Experiment ◽  
Easy Integration ◽  
Tip Displacement

The piezoelectric cantilever resonator is used widely in many fields because of its perfect design, easy-to-control process, easy integration with the integrated circuit. The tip displacement and resonance frequency are two important characters of the piezoelectric cantilever resonator and many models are used to characterize them. However, these models are only suitable for the piezoelectric cantilever with the same width layers. To accurately characterize the piezoelectric cantilever resonators with different width layers, a novel model is proposed for predicting the tip displacement and resonance frequency. The results show that the model is in good agreement with the finite element method (FEM) simulation and experiment measurements, the tip displacement error is no more than 6%, the errors of the first, second, and third-order resonance frequency between theoretical values and measured results are 1.63%, 1.18%, and 0.51%, respectively. Finally, a discussion of the tip displacement of the piezoelectric cantilever resonator when the second layer is null, electrode, or silicon oxide (SiO2) is presented, and the utility of the model as a design tool for specifying the tip displacement and resonance frequency is demonstrated. Furthermore, this model can also be extended to characterize the piezoelectric cantilever with n-layer film or piezoelectric doubly clamped beam.

The Deposition of Silicon Oxide Films by LPCVD at Temperatures as Low as 100°C from a New Liquid Source

1992 ◽  
Vol 282 ◽  
Author(s):  
K. Hochberg ◽  
David A. Roberts
Keyword(s):  
Low Temperature ◽  
Silicon Oxide ◽  
Oxide Films ◽  
Temperature Sensitive ◽  
Oxide Layers ◽  
Low Temperature Deposition ◽  
Liquid Source ◽  
Temperature Deposition ◽  
Higher Temperature

ABSTRACTA precursor for the LPCVD of silicon oxide films has been developed that extends the low temperature deposition range to 100°C. The chemical, 1,4 disilabutane (DSB), produces silicon oxide depositions similar to those of the higher temperature silane and diethylsilane (DES) processes. Optimum DSB processes require pressures below 300 mTorr, similar to silane, in contrast to DES pressures above 600 mTorr at 350°C. This results in poorer conformalities than those of DES, but the step coverages are still superior to those from silane oxides. The DSB films are low stress, carbon-free oxide layers that are suitable for temperature-sensitive underlayers and substrates such as photoresist, plastics, GaAs, and HgCdTe.

Compatibility of CO gas sensitive SnO2/Pt thin film with silicon integrated circuit processing

2000 ◽  
Vol 64 (1-3) ◽  
pp. 49-53 ◽  
Author(s):  
Rajnish K Sharma ◽  
Zhenan Tang ◽  
Philip C.H Chan ◽  
Johnny K.O Sin ◽  
I-Ming Hsing
Keyword(s):  
Thin Film ◽  
Integrated Circuit ◽  
Co Gas ◽  
Integrated Circuit Processing

In SEM a New Method of Internal Micrographic Visualization of Semiconductor Materials and IC by Crossing the Surface

2001 ◽  
Vol 7 (S2) ◽  
pp. 484-485
Author(s):  
Ling Xiao ◽  
Zhuguan Liang ◽  
Yawen Li ◽  
Jian Wang ◽  
Kailin Zhou ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Integrated Circuit ◽  
Silicon Oxide ◽  
Detection Method ◽  
New Method ◽  
Semiconductor Materials ◽  
Contactless Method ◽  
Quality And Reliability ◽  
Nitride Layers ◽  
Scanning Electron

In the paper, we firstly publish a new method of internal micrographic visualization of semiconductor and IC. The quality and reliability of the semiconductor materials (SM) and the integrated circuits (IC) have always been concerned Having a high resolution, high reliable and nondestructive detection method is the key element for their improvements.Silicon oxide layers are used to provide the electrical insulation in the multi-structured ICs. The IC device surfaces are often protected by silicon oxide and silicon nitride layers. Therefore, these insulation layers also cover any inhomogeneity and defect located within the IC devices. It is necessary to have an examining method to detect those defects that are under the insulation layers without damaging the samples. However, the conventional scanning electron microscope (SEM) cannot be utilized to image and examine the surfaces that are positioned below the insulation layers.Novel nondestructive and contactless method has been developed in our laboratory to obtain the internal micrograph that crosses the surface of the semiconductor material and the integrated circuit.

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