A Study on the Mechanism for the Influence of High Density of Defect Movement on the Leakage Current of PN Junction

1990 ◽  
Vol 184 ◽  
Author(s):  
Zhang Tonghe ◽  
Zhou Shenghui ◽  
Wu Yuguang ◽  
Luo Yan
Keyword(s):  
Leakage Current ◽  
Thermal Annealing ◽  
Rapid Thermal Annealing ◽  
Annealing Time ◽  
Defect Density ◽  
Defect Distribution ◽  
High Defect Density ◽  
Pn Junction ◽  
Short Annealing ◽  
Current Reduction

ABSTRACTThe results in the paper show that high defect density appears during rapid thermal annealing. The spreading of the defect distribution increases with increasing of the annealing time. So the leakage current increases up. It is found that the PN junction leakage current for short annealing time(5s) and for hot implantation are obviously lower than that of RT implantation. The mechanism of the leakage current reduction is discussed.

Effect of oxygen on the formation of end-of-range disorder in implantation amorphized silicon

1991 ◽  
Vol 6 (8) ◽  
pp. 1695-1700 ◽  
Author(s):  
E. Lorenz ◽  
J. Gyulai ◽  
L. Frey ◽  
H. Ryssel ◽  
N.Q. Khanh
Keyword(s):  
Thermal Annealing ◽  
Rapid Thermal Annealing ◽  
Defect Structure ◽  
Defect Density ◽  
Low Oxygen ◽  
Continuous Layer ◽  
Float Zone ◽  
Order Of Magnitude ◽  
Visible Effect ◽  
Effect Of Oxygen

Formation of End-of-Range (EOR) disorder was studied in (100)-oriented silicon, when subjected to amorphization by implantation of Ge+ ions, followed by a 10 s Rapid Thermal Annealing (RTA) at 1050 °C. XTEM, RBS/channeling, and SIMS were used to analyze Czochralski grown (CZ) silicon wafers with oxygen concentrations of 6.5, 7.0, and 8.0 × 1017/cm3 and Float Zone (FZ) silicon, as “low oxygen” wafers. Amorphization on neighboring parts of the 4″ wafers was made either by 60 keV Ge+ implantation or by 110 keV Ge+ implantation and by sequential (60 keV + 110 keV) Ge+ implantation. Parts of each wafer were additionally implanted with 13 keV boron. In FZ silicon, no defects were found for 60 keV Ge+ implantation and RTA at 1050 °C. For 110 keV Ge+ and sequential (60 keV + 110 keV) Ge+ implantation in FZ-silicon the majority of the samples showed perfect annealing. Two wafers, however, subjected to sequential implantation still contained defects but with a defect density that was one order of magnitude lower than for CZ wafers. For one of them, not even a continuous layer of defects was formed. In contrast, CZ wafers contained defect bands, except for the 60 keV Ge+ implantation [in accord with the findings of Ozturk et al., IEEE Trans. on Electronic Dev. 35, 659 (1988)]. The presence of boron had no visible effect on the defect structure.

Rapid thermal annealing of Si paste film and pn-junction formation

2020 ◽  
Vol 31 (38) ◽  
pp. 385202
Author(s):  
Huan Zhu ◽  
Morihiro Sakamoto ◽  
Ting Pan ◽  
Takaya Fujisaki ◽  
Hiroshige Matsumoto ◽  
...  
Keyword(s):  
Thermal Annealing ◽  
Rapid Thermal Annealing ◽  
Pn Junction ◽  
Junction Formation

The Effect of Ternary Material (Zr, Y, and O) High-k Gate Dielectrics

2013 ◽  
Vol 699 ◽  
pp. 422-425 ◽  
Author(s):  
K.C. Lin ◽  
C.H. Chou ◽  
J.Y. Chen ◽  
C.J. Li ◽  
J.Y. Huang ◽  
...  
Keyword(s):  
Surface Roughness ◽  
Electrical Property ◽  
Leakage Current ◽  
Thermal Annealing ◽  
Rapid Thermal Annealing ◽  
Gate Dielectrics ◽  
Bottom Layer ◽  
Oxide Thickness ◽  
Equivalent Oxide Thickness ◽  
High K

In this research, the Y2O3 layer is doped with the zirconium through co-sputtering and rapid thermal annealing (RTA) at 550°C, 700°C, and 850°C. Then the Al electrode is deposited to generate two kinds of structures, Al/ZrN/ Y2O3/ Y2O3+Zr/p-Si and Al/ZrN/ Y2O3+Zr/ Y2O3/p-Si. According to the XRD results, when Zr was doped on the upper layer, the crystallization phenomenon was more significant than Zr was at the bottom layer, meaning that Zr may influence the diffusion of the oxygen. The AFM also shows that the surface roughness of Zr has worse performance. For the electrical property, the influence to overall leakage current is increased because the equivalent oxide thickness (EOT) is thinner.

Rapid Thermal Annealing of Ion Implanted p-n Junction in Silicon

1985 ◽  
Vol 52 ◽  
Author(s):  
C. Ho ◽  
R. Kwor ◽  
C. Araujo ◽  
J. Gelpey
Keyword(s):  
Leakage Current ◽  
Thermal Annealing ◽  
Rapid Thermal Annealing ◽  
Dwell Time ◽  
Annealing Temperature ◽  
Current Analysis ◽  
Junction Depth ◽  
Leakage Currents ◽  
Dopant Activation ◽  
Secondary Ion

ABSTRACTThe rapid thermal annealing (RTA) of p+n and n+p diodes, fabricated by the LOCOS process, and its subsequent effects on junction leakage current, junction depth and dopant activation were investigated. The reverse bias diode leakage currents of implanted Si <100> samples (As+: 60 KeY, 5×1014 5×1015 cm−2, B+: 25 KeV, l×1014, l×1015 cm−2 and BF2+: 45 KeV, 1×1015cm−2 ) were measured as functions of annealing temperature, and dwell time. The annealing was performed using an Eaton RTA system (Nova ROA-400) at temperatures ranging from 950 °C to 1150 °C. Annealing times ranged from 0.2 sec. to 10 sec. The results from the diode leakage current analysis are correlated with those from Secondary Ion Mass Spectroscopy (SIMS) and differential Hall measurements. The reverse-biased leakage currents from the RTA-treated samples are compared with those from furnace-annealed samples.

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