Cmos Polysilicon Thin Film Transistors with Simultaneously Deposited Layers for Source-Drain and Gate

A new process architecture for fabricating CMOS thin film transistors (TFTs) using in-situ-doped polysilicon source-drain layers is proposed. In the new architecture, a top-gate n-channel TFT and a bottom-gate p-channel TFT, or vice versa, form a CMOS pair. This allows an n+ - doped polysilicon bottom (or top) layer to serve simultaneously as the source-drain layer of the n-channel TFTs and the gate layer of the p-channel TFTs; while a p+ - doped polysilicon top (or bottom) layer serves as the source-drain layer of the p-channel TFT and the gate layer of the n-channel TFT. It thus eliminates the deposition of a separate doped gate layer normally required in the conventional process flow. In addition, a thin tri-layer stack, consisting of undoped-poly / gate dielectric / undoped-poly, separates the two doped polysilicon layers, thus allowing the use of a single island mask to define the channel regions for both the n- and p-channel TFTs. As a result, the photolithographic steps are also reduced by one mask. Working n- and p-channel TFTs with both top- and bottomgate structures, obtained by reversing the dopant types of the top and the bottom layers, have been successfully demonstrated using low-temperature (< 600 °C) polysilicon technology.