Effect of the MOS Process on the Work-Function Difference Between the Polysilicon Gates and the Silicon Substrate

1990 ◽  
Vol 182 ◽  
Author(s):  
N. Lifshitz
Keyword(s):  
Integrated Circuit ◽  
Silicon Substrate ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Process Variations ◽  
Polysilicon Gate ◽  
Effect Transistor ◽  
Work Function Difference ◽  
Circuit Technology ◽  
Function Difference

AbstractPolysilicon gates are an important element of modem MOS integrated circuit technology. The workfunction difference (ϕps) between the polysilicon gate and the silicon substrate is a vital parameter of the MOS system because it determines the threshold voltage of the field-effect transistor. Ideally, ϕps is determined by the doping level in both polysilicon and the substrate. In reality process variations influence the ϕPS in a tangible way. Some of these effects are reviewed in the present paper.

Preparation of TEM samples by focused ion beams

1995 ◽  
Vol 53 ◽  
pp. 518-519
Author(s):  
John F. Walker ◽  
J C Reiner ◽  
C Solenthaler
Keyword(s):  
Integrated Circuit ◽  
Polycrystalline Silicon ◽  
Field Effect Transistor ◽  
High Spatial Resolution ◽  
Ion Beam ◽  
Ion Beams ◽  
Focused Ion Beams ◽  
Precise Location ◽  
Effect Transistor ◽  
Circuit Technology

The high spatial resolution available from TEM can be used with great advantage in the field of microelectronics to identify problems associated with the continually shrinking geometries of integrated circuit technology. In many cases the location of the problem can be the most problematic element of sample preparation. Focused ion beams (FIB) have previously been used to prepare TEM specimens, but not including using the ion beam imaging capabilities to locate a buried feature of interest. Here we describe how a defect has been located using the ability of a FIB to both mill a section and to search for a defect whose precise location is unknown. The defect is known from electrical leakage measurements to be a break in the gate oxide of a field effect transistor. The gate is a square of polycrystalline silicon, approximately 1μm×1μm, on a silicon dioxide barrier which is about 17nm thick. The break in the oxide can occur anywhere within that square and is expected to be less than 100nm in diameter.

InGaAs/Si Heterojunction Tunneling Field-Effect Transistor on Silicon Substrate

2014 ◽  
Vol E97.C (7) ◽  
pp. 677-682
Author(s):  
Sung YUN WOO ◽  
Young JUN YOON ◽  
Jae HWA SEO ◽  
Gwan MIN YOO ◽  
Seongjae CHO ◽  
...  
Keyword(s):  
Silicon Substrate ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Effect Transistor

scholarly journals 4H-SiC Double Trench MOSFET with Split Heterojunction Gate for Improving Switching Characteristics

Materials ◽  
2021 ◽  
Vol 14 (13) ◽  
pp. 3554
Author(s):  
Jaeyeop Na ◽  
Jinhee Cheon ◽  
Kwangsoo Kim
Keyword(s):  
Dynamic Characteristics ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Switching Loss ◽  
Switching Speed ◽  
Polysilicon Gate ◽  
Effect Transistor ◽  
Switching Characteristics

In this paper, a novel 4H-SiC split heterojunction gate double trench metal-oxide-semiconductor field-effect transistor (SHG-DTMOS) is proposed to improve switching speed and loss. The device modifies the split gate double trench MOSFET (SG-DTMOS) by changing the N+ polysilicon split gate to the P+ polysilicon split gate. It has two separate P+ shielding regions under the gate to use the P+ split polysilicon gate as a heterojunction body diode and prevent reverse leakage `current. The static and most dynamic characteristics of the SHG-DTMOS are almost like those of the SG-DTMOS. However, the reverse recovery charge is improved by 65.83% and 73.45%, and the switching loss is improved by 54.84% and 44.98%, respectively, compared with the conventional double trench MOSFET (Con-DTMOS) and SG-DTMOS owing to the heterojunction.

scholarly journals Leakage Mitigation in NW FET using Negative Schottky Junction Drain and its Process Variation Analysis

2021 ◽  
Author(s):  
Mohd Rizwan Uddin Shaikh ◽  
Sajad A Loan ◽  
Abdullah G Alharbi
Keyword(s):  
Field Effect ◽  
Field Effect Transistor ◽  
Schottky Barrier Height ◽  
Process Variation ◽  
Process Variations ◽  
Schottky Junction ◽  
Variation Analysis ◽  
Drain Side ◽  
Band To Band Tunneling ◽  
Effect Transistor

Abstract In this work, a Schottky junction on the drain side employing low workfunction (WF) metal is proposed as a method to suppress the OFF-state leakage in nanowire (NW) field-effect transistor (FET). Instead of a highly n+ doped drain, low WF metal with negative electron Schottky-barrier height (SBH) as a drain minimizes the lateral band-to-band tunneling (L-BTBT) considerably. L-BTBT is the movement of carriers (holes) from the drain conduction band (CB) into the channel valence band (VB) during the OFF-state. Impact of varying WF at channel-drain junction on the device characteristics is studied. It is observed that SBH60 eV is required to mitigate L-BTBT compared to the conventionally-doped and junctionless (JL) NW counterpart. Furthermore, unlike L-BTBT, leakage in NW Schottky-drain (SD) comprises of holes tunneling through the SB from the metal drain into the channel and termed as the lateral SB tunneling (L-SBT). In contrast to JL NW FET, the process variation immunity (varying channel doping, NCh and NW diameter, dNW ) and the ON-state current of the proposed device is not compromised at the expense of lower OFF-state LSBT. Instead, the device is less susceptible to process variations and retains the ON-state performance of the NW MOSFET. For a ±20% change in NCh, ∆IOF F /IOF F of 7% compared to 97% in NW JL FET is observed.

Sign in / Sign up

Export Citation Format

Share Document