Impact of Various Polysilicon Deposition Process on Thin Gate-Oxide Properties in Submicron CMOS Technology

1990 ◽  
Vol 182 ◽  
Author(s):  
P. K. Roy ◽  
T. Kook ◽  
V. C. Kannan ◽  
G. J. Felton ◽  
R. A. Powell ◽  
...  
Keyword(s):  
Breakdown Strength ◽  
Defect Density ◽  
Chemical Vapor ◽  
Gate Oxide ◽  
Deposition Process ◽  
Cmos Technology ◽  
Ex Situ ◽  
Cmos Process ◽  
Submicron Cmos ◽  
Deposition Processes

AbstractThe dielectric quality (defect density, Do and breakdown strength, Fbd) of 150Å SiO2 gate oxide (GOX) films grown by conventional or stacked oxidation scheme are discussed from the leakage measurements of polysilicon capacitors on test structure simulating our submicron CMOS process. Various polysilicon (poly) deposition processes from silane pyrolysis (570°C -620°C) were used by the low pressure chemical vapor deposition (LPCVD) technique. Both in situ and ex situ poly doping by phosphorus (P) were used to ascertain their impact on the GOX properties. The substructural characteristics of the poly/SiO2 and SiO2/Si interfaces generated by various combinations of GOX and poly deposition processes were done by the high resolution TEM lattice fringe technique under phase contrast mode.

High Temperature Reliability Investigations up to 350 °C of Gate Oxide Capacitors realized in a Silicon-on-Insulator CMOS-Technology

2013 ◽  
Vol 2013 (HITEN) ◽  
pp. 000116-000121
Author(s):  
K. Grella ◽  
S. Dreiner ◽  
H. Vogt ◽  
U. Paschen
Keyword(s):  
High Temperature ◽  
Dielectric Breakdown ◽  
Gate Oxide ◽  
Oxide Thickness ◽  
Cmos Technology ◽  
Silicon On Insulator ◽  
Cmos Process ◽  
Oxide Breakdown ◽  
Time Dependent Dielectric Breakdown ◽  
Single Poly Eeprom

Standard Bulk-CMOS-technology targets use-temperatures of not more than 175 °C. With Silicon-on-Insulator-technologies (SOI), digital and analog circuitry is possible up to 250 °C and even more, but performance and reliability are strongly affected at these high temperatures. One of the main critical factors is the gate oxide quality and its reliability. In this paper, we present a study of gate oxide capacitor time-dependent dielectric breakdown (TDDB) measurements at temperatures up to 350 °C. The experiments were carried out on gate oxide capacitor structures which were realized in the Fraunhofer 1.0 μm SOI-CMOS process. This technology is based on 200 mm wafers and features, among others, three layers of tungsten metallization with excellent reliability concerning electromigration, voltage independent capacitors, high resistance resistors, and single-poly-EEPROM cells. The gate oxide thickness is 40 nm. Using the data of the TDDB-measurements, the behavior of field and temperature acceleration parameters at temperatures up to 350 °C was evaluated. For a more detailed investigation, the current evolution in time was also studied. An analysis of the oxide breakdown conditions, in particular the field and temperature dependence of the charge to breakdown and the current just before breakdown, completes the study. The presented data provide important information about accelerated oxide reliability testing beyond 250 °C, and make it possible to quickly evaluate the reliability of high temperature CMOS-technologies at use-temperature.

In-Situ Observation of Chemical Vapor Deposition of Thin Sige Films by Optical Reflection Interferometry

1994 ◽  
Vol 375 ◽  
Author(s):  
G. Ritter ◽  
B. Tillack ◽  
M. Weidner ◽  
F. G. Böbel ◽  
B. Hertel
Keyword(s):  
Chemical Vapor Deposition ◽  
Vapor Deposition ◽  
Chemical Vapor ◽  
Deposition Process ◽  
Ex Situ ◽  
In Situ Observation ◽  
Optical Reflection ◽  
Initial Stage

AbstractChemical Vapor Deposition of Si1-x Gex – films on Si (100) and of polycrystalline Si1-x Gex, layers on SiO2 – coated substrates have been performed at a pressure of 200 Pa in the temperature range of 500°C – 800°C, correspondingly. To observe the growth process and to characterize the growing thin films at deposition conditions an optical reflection interferometer (PYRITIERS) has been used. Comparing the data obtained at growth temperature with ex- situ measurements by spectroscopic ellipsometry the temperature dependence of optical constants of SiGe films have been evaluated. The reflectivity measurements during the deposition process allow to study the quality of the heteroepitaxial film, even in the initial stage of epitaxial growth.

He plus remote plasma nitridation of ultra-thin gate oxide for deep submicron CMOS technology applications

2001 ◽  
Vol 37 (12) ◽  
pp. 788 ◽  
Author(s):  
Shyh-Fann Ting ◽  
Yean-Kuen Fang ◽  
Chien-Hao Chen ◽  
Chih-Wei Yang ◽  
Mo-Chiun Yu ◽  
...  
Keyword(s):  
Gate Oxide ◽  
Cmos Technology ◽  
Deep Submicron ◽  
Remote Plasma ◽  
Plasma Nitridation ◽  
Technology Applications ◽  
Submicron Cmos ◽  
Thin Gate Oxide

scholarly journals Nanotopographical control of surfaces using chemical vapor deposition processes

2017 ◽  
Vol 8 ◽  
pp. 1250-1256 ◽  
Author(s):  
Meike Koenig ◽  
Joerg Lahann
Keyword(s):  
Vapor Deposition ◽  
Three Dimensional ◽  
Chemical Vapor ◽  
Deposition Process ◽  
Polymer Coatings ◽  
Oblique Angle ◽  
Concise Review ◽  
Deposition Processes ◽  
Deposition Techniques ◽  
Post Deposition

In recent years much work has been conducted in order to create patterned and structured polymer coatings using vapor deposition techniques – not only via post-deposition treatment, but also directly during the deposition process. Two-dimensional and three-dimensional structures can be achieved via various vapor deposition strategies, for instance, using masks, exploiting surface properties that lead to spatially selective deposition, via the use of additional porogens or by employing oblique angle polymerization deposition. Here, we provide a concise review of these studies.

Reliability Investigations up to 350°C of Gate Oxide Capacitors Realized in a Silicon-on-Insulator CMOS Technology

2013 ◽  
Vol 10 (4) ◽  
pp. 150-154 ◽  
Author(s):  
K. Grella ◽  
S. Dreiner ◽  
H. Vogt ◽  
U. Paschen
Keyword(s):  
Dielectric Breakdown ◽  
Gate Oxide ◽  
Oxide Thickness ◽  
Cmos Technology ◽  
Silicon On Insulator ◽  
Cmos Process ◽  
Leakage Currents ◽  
Oxide Breakdown ◽  
Time Dependent Dielectric Breakdown ◽  
Operation Temperature

It is difficult to use standard bulk-CMOS-technology at temperatures higher than 175°C due to high pn-leakage currents. Silicon-on-insulator-technologies (SOI), on the other hand, are usable up to 250°C and even higher, because leakage currents can be reduced by two to three orders of magnitude. Nevertheless, performance and reliability of SOI devices are strongly affected at these high temperatures. One of the main critical factors is the gate oxide quality and its reliability. In this paper, we present a study of gate oxide capacitor time-dependent dielectric breakdown (TDDB) measurements at temperatures up to 350°C. The experiments were carried out on gate oxide capacitor structures realized in the Fraunhofer 1.0 μm SOI-CMOS process. The gate oxide thickness is 40 nm. Using the data of the TDDB measurements, the behavior of field and temperature acceleration parameters at temperatures up to 350°C was evaluated. For a more detailed investigation, the evolution of the current in time was also studied. An analysis of the oxide breakdown conditions, in particular the field and temperature dependence of the charge to breakdown and the current just before breakdown, completes the study. The presented data provide important information about accelerated oxide reliability testing beyond 250°C, and make it possible to quickly evaluate the reliability of high temperature CMOS technologies at operation temperature.

Effect of the pre-gate oxide cleaning temperature on the reliability of GOI and devices performances in deep submicron CMOS technology

2008 ◽  
Vol 48 (11-12) ◽  
pp. 1786-1790 ◽  
Author(s):  
Y.T. Chiang ◽  
Y.K. Fang ◽  
Y.J. Huang ◽  
T.H. Chou ◽  
S.Y. Yeh ◽  
...  
Keyword(s):  
Gate Oxide ◽  
Cmos Technology ◽  
Deep Submicron ◽  
Submicron Cmos

scholarly journals Growth Mechanism of a Hybrid Structure Consisting of a Graphite Layer on Top of Vertical Carbon Nanotubes

2012 ◽  
Vol 2012 ◽  
pp. 1-10 ◽  
Author(s):  
Nicolo' Chiodarelli ◽  
Cigang Xu ◽  
Olivier Richard ◽  
Hugo Bender ◽  
Alexander Klekachev ◽  
...  
Keyword(s):  
Carbon Nanotubes ◽  
Chemical Vapor ◽  
Deposition Process ◽  
Growth Conditions ◽  
Hybrid Structure ◽  
Carbon Layer ◽  
Time Dynamic ◽  
Catalyst Film ◽  
Optical And Electronic Properties ◽  
Deposition Processes

Graphene and carbon nanotubes (CNTs) are both carbon-based materials with remarkable optical and electronic properties which, among others, may find applications as transparent electrodes or as interconnects in microchips, respectively. This work reports on the formation of a hybrid structure composed of a graphitic carbon layer on top of vertical CNT in a single deposition process. The mechanism of deposition is explained according to the thickness of catalyst used and the atypical growth conditions. Key factors dictating the hybrid growth are the film thickness and the time dynamic through which the catalyst film dewets and transforms into nanoparticles. The results support the similarities between chemical vapor deposition processes for graphene, graphite, and CNT.

Deep Submicron CMOS Technology Using Top-Edge Round STI and Dual Gate Oxide for Low Power 256 M-Bit Mobile DRAM

2003 ◽  
Vol 42 (Part 1, No. 4B) ◽  
pp. 1892-1896 ◽  
Author(s):  
Chihoon Lee ◽  
Donggun Park ◽  
Namhyuk Jo ◽  
Chanseong Hwang ◽  
Hyeong Joon Kim ◽  
...  
Keyword(s):  
Low Power ◽  
Gate Oxide ◽  
Cmos Technology ◽  
Deep Submicron ◽  
Dual Gate ◽  
Submicron Cmos

scholarly journals Deposition Methods for Microstructured and Nanostructured Coatings on Metallic Bone Implants: A Review

2017 ◽  
Vol 2017 ◽  
pp. 1-9 ◽  
Author(s):  
Bailey Moore ◽  
Ebrahim Asadi ◽  
Gladius Lewis
Keyword(s):  
Plasma Spray ◽  
Vapor Deposition ◽  
Physical Vapor Deposition ◽  
Chemical Vapor ◽  
Aerosol Deposition ◽  
Deposition Process ◽  
Future Research ◽  
Bone Implants ◽  
Implant Surface ◽  
Deposition Processes

A review of current deposition processes is presented as they relate to osseointegration of metallic bone implants. The objective is to present a comprehensive review of different deposition processes used to apply microstructured and nanostructured osteoconductive coatings on metallic bone implants. Implant surface topography required for optimal osseointegration is presented. Five of the most widely used osteoconductive coating deposition processes are reviewed in terms of their microstructure and nanostructure, usable thickness, and cost, all of which are summarized in tables and charts. Plasma spray techniques offer cost-effective coatings but exhibit deficiencies with regard to osseointegration such as high-density, amorphous coatings. Electrodeposition and aerosol deposition techniques facilitate the development of a controlled-microstructure coating at a similar cost. Nanoscale physical vapor deposition and chemical vapor deposition offer an alternative approach by allowing the coating of a highly structured surface without significantly affecting the microstructure. Various biomedical studies on each deposition process are reviewed along with applicable results. Suggested directions for future research include further optimization of the process-microstructure relation, crystalline plasma spray coatings, and the deposition of discrete coatings by additive manufacturing.

Morphology Of Silicon Oxides On Silicon Carbide

1997 ◽  
Vol 483 ◽  
Author(s):  
M. L. O‘Brien ◽  
S. Pejdo ◽  
R. J. Nemanich
Keyword(s):  
Silicon Carbide ◽  
Nitrous Oxide ◽  
Formation Process ◽  
Growth Process ◽  
Chemical Vapor ◽  
Deposition Process ◽  
Oxide Formation ◽  
Oxide Deposition ◽  
Control Wafers ◽  
Deposition Processes

AbstractThe development of high power devices based on silicon carbide requires a more complete understanding of the oxide formation process and interface characteristics. By using an integrated UHV system, samples were cleaned and oxides deposited in situ. The approach of the oxide formation process was to form the initial insulator, a few angstroms thick, and then deposit an oxide. Various deposition techniques are used in the oxide growth process; both thermal and plasma enhanced chemical vapor deposition were employed with two different precursors (oxygen and nitrous oxide), and the results were compared with thermal oxidation. The morphology of each of the deposited oxides was compared to the bare substrate and the thermal oxide wafers. This study focuses on the morphology of the different deposition processes using AFM. Examination of the morphology of the initial insulator growth process and the oxide deposition process gives insight into the physical characteristics of the silicon dioxide deposited on silicon carbide. The RMS values of the initial insulator formation and the control wafers are 0.93 and 0.95 nm respectively. Meanwhile, the RMS values for PECVD (200–400°C) and thermal CVD (400–600°C for oxygen-silane and 800–1000°C for nitrous oxide-silane) range from 1.43 to 1.93 nm.

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