Au Ohmic Contacts to P-Type Hg1-xCdxte Utilizing Thin Interfacial Layers

1990 ◽  
Vol 181 ◽  
Author(s):  
V. Krishnamurthy ◽  
A. Simmons ◽  
C. R. Helms

ABSTRACTOhmic behavior is observed in electroless Au contacts to p -type Hg1−xCdxTe. Our investigation of the interfacial chemistry of such contacts suggest that this ohmic behavior may be due to the presence of a Te,O, and CI layer. To verify this correlation with interfacial chemistry, thin plasma oxide layers were used in evaporated Au contacts. The annealed plasma oxidized contacts exhibited low contact resistances. This behavior was attributed to a low interface state density at the interfacial layer/Hg1−xCdxTe interface. In comparison, as-deposited and annealed Au contacts without a thin interfacial layer were rectifying with a large barrier height.

2013 ◽  
Vol 133 (7) ◽  
pp. 1279-1284
Author(s):  
Takuro Iwasaki ◽  
Toshiro Ono ◽  
Yohei Otani ◽  
Yukio Fukuda ◽  
Hiroshi Okamoto

2015 ◽  
Vol 98 (6) ◽  
pp. 8-15
Author(s):  
TAKURO IWASAKI ◽  
TOSHIRO ONO ◽  
YOHEI OTANI ◽  
YUKIO FUKUDA ◽  
HIROSHI OKAMOTO

2013 ◽  
Vol 34 (5) ◽  
pp. 052002 ◽  
Author(s):  
Jiahong Zhang ◽  
Qingquan Liu ◽  
Yixian Ge ◽  
Fang Gu ◽  
Min Li ◽  
...  

2001 ◽  
Vol 670 ◽  
Author(s):  
Mark A. Shriver ◽  
Ann M. Gabrys ◽  
T. K. Higman ◽  
S. A. Campbell

ABSTRACTCurrent high permittivity material deposition techniques produce a low permittivity oxide interfacial layer consequently increasing the equivalent oxide thickness. This interfacial oxide layer can be prevented by initially growing a thin nitride layer to act as a diffusion barrier. The interfacial nitride layer must also have low interface state densities comparable to state-of-the-art SiO2 insulators in order to be suitable for MOSFETs. The nitride layer used in this study was formed by thermal nitridation in a UHV system, with the subsequent high permittivity deposition done in an adjoining system. After forming capacitors from these films, capacitance vs. voltage (C-V) techniques were used to determine the interface state density and equivalent oxide thickness of the films. Gate stack films were produced on Si(100) and Si(111) and the results are compared. Gate stacks on Si(100) show a slight increase in stretchout in the high frequency C-V curves for both n-type and p-type samples. Initial data suggests that Si(111) has a lower interface state density than the Si(100) gate stacks. This may be attributed to the Si3N4layer on Si(111) being epitaxial nitride.


2017 ◽  
Vol 8 (3) ◽  
pp. 035016
Author(s):  
Adison Nopparuchikun ◽  
Nathaporn Promros ◽  
Phongsaphak Sittimart ◽  
Peeradon Onsee ◽  
Asanlaya Duangrawa ◽  
...  

1996 ◽  
Vol 69 (2) ◽  
pp. 230-232 ◽  
Author(s):  
Zhi Chen ◽  
Dae‐Gyu Park ◽  
Francke Stengal ◽  
S. Noor Mohammad ◽  
Hadis Morkoç

2019 ◽  
Vol 40 (2) ◽  
pp. 174-176
Author(s):  
Yi-He Tsai ◽  
Chen-Han Chou ◽  
Yun-Yan Chung ◽  
Wen-Kuan Yeh ◽  
Yu-Hsien Lin ◽  
...  

2006 ◽  
Vol 527-529 ◽  
pp. 1525-1528
Author(s):  
W. Huang ◽  
T. Khan ◽  
T. Paul Chow

Both n-type and p-type GaN MOS capacitors with plasma-enhanced CVD-SiO2 as the gate oxide were characterized using both capacitance and conductance techniques. From a n type MOS capacitor, an interface state density of 3.8×1010/cm2-eV was estimated at 0.19eV near the conduction band and decreases deeper into the bandgap while from a p type MOS capacitor, an interface state density of 1.4×1011/cm2-eV 0.61eV above the valence band was estimated and decreases deeper into the bandgap. Unlike the symmetric interface state density distribution in Si, an asymmetric interface state density distribution with lower density near the conduction band and higher density near the valence band has been determined.


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