Polyimide-Ceramic Substrate for Supercomputer Packaging

1989 ◽  
Vol 167 ◽  
Author(s):  
K. Kimbara ◽  
A. Dohya ◽  
T. Watari
Keyword(s):  
High Power ◽  
High Speed ◽  
High Performance ◽  
General Purpose ◽  
High Density ◽  
Ceramic Substrate ◽  
Liquid Cooling ◽  
General Purpose Computer ◽  
Performance System ◽  
Cooling Module

AbstractThis paper introduces the Polylmide-Ceramic substrate for NEC SX Supercomputers. In case of high performance system such as supercomputers and top end machines in general purpose computer, sophisticated packaging technologies are essential to achieve fastest operations as well as to use highestspeed, highly integrated LSIs.Wiring substrate which mounts and interconnects LSIs is the key to back up LSI's higher logical-operations.The high speed interconnection wirings and high density LSI mounting are requested for substrate.The Polyimide-Ceramic substrate had been developed to meet these demands and have many features of high density thin film wiring, high power supply, high thermal conductivity and huge number of I/Os, in addition to high speed wiring.25μm wide 75μm center-to-center spacing, two signal layers, 6ns/m signal transmissions, 2.5W/cm2 high power density, 2177 I/Os on a 100mm square substrate have been achieved by using this super substrate technology.The packaging hierarchy, the first level packaging of TAB LSI, the second level of multi-chip packaging by using Polyimide-Ceramic substrate and liquid cooling module, and the third level of board assemblies are introduced.

scholarly journals A Review on the Fabrication and Reliability of Three-Dimensional Integration Technologies for Microelectronic Packaging: Through-Si-Via and Solder Bumping Process

Metals ◽  
2021 ◽  
Vol 11 (10) ◽  
pp. 1664
Author(s):  
Do Hoon Cho ◽  
Seong Min Seo ◽  
Jang Baeg Kim ◽  
Sri Harini Rajendran ◽  
Jae Pil Jung
Keyword(s):  
High Speed ◽  
High Performance ◽  
New Technologies ◽  
Three Dimensional ◽  
High Density ◽  
Internal Stresses ◽  
Deep Reactive Ion Etching ◽  
Fifth Generation ◽  
Precise Understanding ◽  
Fabrication Defects

With the continuous miniaturization of electronic devices and the upcoming new technologies such as Artificial Intelligence (AI), Internet of Things (IoT), fifth-generation cellular networks (5G), etc., the electronics industry is achieving high-speed, high-performance, and high-density electronic packaging. Three-dimensional (3D) Si-chip stacking using through-Si-via (TSV) and solder bumping processes are the key interconnection technologies that satisfy the former requirements and receive the most attention from the electronic industries. This review mainly includes two directions to get a precise understanding, such as the TSV filling and solder bumping, and explores their reliability aspects. TSV filling addresses the DRIE (deep reactive ion etching) process, including the coating of functional layers on the TSV wall such as an insulating layer, adhesion layer, and seed layer, and TSV filling with molten solder. Solder bumping processes such as electroplating, solder ball bumping, paste printing, and solder injection on a Cu pillar are discussed. In the reliability part for TSV and solder bumping, the fabrication defects, internal stresses, intermetallic compounds, and shear strength are reviewed. These studies aimed to achieve a robust 3D integration technology effectively for future high-density electronics packaging.

COMPUTER AND PROGRAMS FOR THE AP-C ANALYTICAL STEREOPLOTTER

1963 ◽  
Vol 17 (2) ◽  
pp. 155-168 ◽  
Author(s):  
E. C. Johnson ◽  
V. C. Kamm
Keyword(s):  
High Speed ◽  
General Purpose ◽  
Medium Size ◽  
Control Computer ◽  
General Purpose Computer ◽  
Complete Set ◽  
Purpose Computer

Tbe AP/C control computer is a specially designed, high speed, serial, binary, general-purpose machine with approximately 2000 words of memory. Although the machine is basically a general-purpose computer, in includes special facilities for communicating with the operator of the AP/C Stereoplotter for inputs from the operator’s handwheels and footwheel, and for outputs to servomechanisms on the AP/C viewing unit and coordinatograph. A complete set of programs for inner, relative and absolute orientations and for plotting operations is provided. In addition, the computer may be used for general-purpose computing when not required for plotting. In speed and versatility it is superior to most medium-size commercial computers.

HIGH PERFORMANCE ECL-BiCMOS TECHNOLOGY

1993 ◽  
Vol 04 (03) ◽  
pp. 283-299
Author(s):  
T. M. LIU ◽  
R. G. SWARTZ ◽  
T.Y. CHIU
Keyword(s):  
High Speed ◽  
High Performance ◽  
Process Integration ◽  
High Density ◽  
Bipolar Devices ◽  
Bipolar Technology ◽  
Bicmos Technology ◽  
Bipolar Circuit

With the increasing maturity of conventional Bipolar-CMOS (BiCMOS) technologies, a new category of BiCMOS called "ECL-BiCMOS" or high performance BiCMOS technology has emerged. These ECL-BiCMOS technologies offer not only high density CMOS capability, but also feature high speed bipolar devices for emitter couple logic (ECL) and mixed analog/digital applications. Since many process requirements of advanced bipolar technology differ from those of CMOS, to fabricate high speed bipolar devices without compromising CMOS performance is the primary challenge. In this paper, we discuss key process integration issues and review various approaches. In particular, we describe a recently developed half-micron super self-aligned BiCMOS technology. Together with high density/high speed CMOS, multi-GHz communication bipolar circuit results are presented to show the potential of high performance BiCMOS technology.

scholarly journals Introduction to the Special Issue on Digital Signal Processing in Radio Astronomy

2016 ◽  
Vol 05 (04) ◽  
pp. 1602002 ◽  
Author(s):  
D. C. Price ◽  
J. Kocz ◽  
M. Bailes ◽  
L. J. Greenhill
Keyword(s):  
Signal Processing ◽  
Digital Signal Processing ◽  
Radio Astronomy ◽  
Graphics Processing Units ◽  
High Speed ◽  
High Performance ◽  
Digital Signal ◽  
General Purpose ◽  
Special Issue ◽  
Dsp Systems

Advances in astronomy are intimately linked to advances in digital signal processing (DSP). This special issue is focused upon advances in DSP within radio astronomy. The trend within that community is to use off-the-shelf digital hardware where possible and leverage advances in high performance computing. In particular, graphics processing units (GPUs) and field programmable gate arrays (FPGAs) are being used in place of application-specific circuits (ASICs); high-speed Ethernet and Infiniband are being used for interconnect in place of custom backplanes. Further, to lower hurdles in digital engineering, communities have designed and released general-purpose FPGA-based DSP systems, such as the CASPER ROACH board, ASTRON Uniboard, and CSIRO Redback board. In this introductory paper, we give a brief historical overview, a summary of recent trends, and provide an outlook on future directions.

Integrated Navigation by Least Square Adjustment

1970 ◽  
Vol 23 (2) ◽  
pp. 174-186 ◽  
Author(s):  
Karl Ramsayer
Keyword(s):  
High Speed ◽  
Dead Reckoning ◽  
General Purpose ◽  
Least Square ◽  
Integrated Navigation ◽  
General Purpose Computer ◽  
Navigational Aids ◽  
Navigational System ◽  
Available Information ◽  
Navigational Systems

For the integration of different navigational aids of an aircraft by a general purpose computer the following way is proposed: The basic navigational system is a doppler or inertial dead reckoning system (D.R.S.). The other navigational aids serve for control measurements, with the help of which the error of the D.R.-position and the most important systematic error sources of the D.R.S. are determined by least square adjustment during flight. These error quantities are then used for a corresponding correction of the D.R.S. The supplementary navigational aids are consequently used both for the correction of the D.R. position and for the calibration of the D.R.S. The method is described for the example of the integration of a doppler D.R.S. with Tacan.From the great number of different navigational aids, which are today available or in development, we can draw the conclusion that none of these navigational systems can satisfy all requirements. Therefore, for many years it has been the custom to combine several navigational aids, and thus the human navigator has the task of evaluating the different navigational information. This evaluation is, however, often disturbed by unfavourable conditions. In a high-speed aircraft for example the navigator is overburdened by a lack of time and space, errors in the navigational sensors, &c. This necessarily means that the evaluation of the data is reduced to a minimum, and that a great deal of the available information is lost.

scholarly journals Performance Analysis of Parallelized Bioinformatics Applications

2018 ◽  
Vol 7 (2) ◽  
pp. 70-74
Author(s):  
Dhruv Chander Pant ◽  
O. P. Gupta
Keyword(s):  
Distributed Computing ◽  
High Performance ◽  
Low Cost ◽  
General Purpose ◽  
Computational Power ◽  
Genome Data ◽  
Technological Developments ◽  
General Purpose Computer ◽  
Performance Computing ◽  
Purpose Computer

The main challenges bioinformatics applications facing today are to manage, analyze and process a huge volume of genome data. This type of analysis and processing is very difficult using general purpose computer systems. So the need of distributed computing, cloud computing and high performance computing in bioinformatics applications arises. Now distributed computers, cloud computers and multi-core processors are available at very low cost to deal with bulk amount of genome data. Along with these technological developments in distributed computing, many efforts are being done by the scientists and bioinformaticians to parallelize and implement the algorithms to take the maximum advantage of the additional computational power. In this paper a few bioinformatics algorithms have been discussed. The parallelized implementations of these algorithms have been explained. The performance of these parallelized algorithms has been also analyzed. It has been also observed that in parallel implementations of the various bioinformatics algorithms, impact of communication subsystems with respect to the job sizes should also be analyzed.

Novel Nanometric Reversible Low Power Bidirectional Universal Logarithmic Barrel Shifter with Overflow and Zero Flags

2015 ◽  
Vol 24 (04) ◽  
pp. 1550049 ◽  
Author(s):  
Nayereh Hosseininia ◽  
Soudabeh Boroumand ◽  
Majid Haghparast
Keyword(s):  
Low Power ◽  
High Speed ◽  
High Performance ◽  
Error Control ◽  
Digital Signal ◽  
General Purpose ◽  
Vlsi Circuits ◽  
Quantum Cost ◽  
Hardware Complexity ◽  
Barrel Shifter

One of the most important issues in designing VLSI circuits is power consumption. Reversible logic which is widely utilized in quantum computing, low power CMOS design, optical information processing, bioinformatics and nanotechnology-based systems decreases power loss. A reversible circuit has zero internal power dissipation because it does not lose information. Reversible barrel shifters are required to construct reversible embedded digital signal and general-purpose processors. Data shifting is often used in high-speed/low-power error-control applications, floating point normalization, address decoding and bit indexing. This paper proposes a novel reversible bidirectional universal barrel shifter which is applied in high speed and high performance applications. The proposed barrel shifter is designed in a single circuit with overflow and zero flags. It performs three operations consisting of rotating, logical and arithmetic shifting that transfers and shifts data in both directions. The design is evaluated and formulated in terms of number of garbage outputs, number of constant inputs, quantum cost, number of reversible gates and hardware complexity. All the scales are in nanometric area.

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