Generation of Blind Via-Holes for a High Density Multi-Chip-Module Using Excimer Lasers

1989 ◽  
Vol 158 ◽  
Author(s):  
Friedrich G. Bachmann
Keyword(s):  
Large Scale ◽  
Printed Circuit Board ◽  
High Density ◽  
Circuit Board ◽  
Excimer Lasers ◽  
Signal Delay ◽  
Delay Times ◽  
Via Holes ◽  
On Chip ◽  
First Time

ABSTRACTIn recent years the on-chip delay has gone down much more rapidly than the signal delay in packaged circuits. As a consequence of this the packaging delay times have had to be reduced drastically, which means that a greater packging density had to be implemented. A novel planar packaging technique, used in the new Siemens main frame computer 7500 H 90 has led to considerable progress in solving this problem. An essential part of this system is a multi-chip-module which can hold up to 144 bare chips. The carrier of these IC's is a 16-layer high density multilayer printed circuit board, which is fabricated in a sequential process. Interlayer contacts are formed by 80 µm wide blind via-holes, which are generated by excimer-laser ablation of the dielectric. The process desribed in this paper shows that it is possible to produce blind via-holes with an aspect ratio of about one in an extremely reliable and reproducible way. This process is already being successfully run on a production line. It is to our best knowledge the first time excimer lasers have been used on a large-scale in an industrial environment.

Excimer Laser Drill for Multilayer Printed Circuit Boards: From Advanced Development to Factory Floor

MRS Bulletin ◽  
1989 ◽  
Vol 14 (12) ◽  
pp. 49-53 ◽  
Author(s):  
Friedrich Bachmann
Keyword(s):  
Excimer Laser ◽  
High Speed ◽  
Large Scale ◽  
Printed Circuit Boards ◽  
Printed Circuit Board ◽  
Circuit Board ◽  
Multichip Module ◽  
Circuit Boards ◽  
Printed Circuit ◽  
Delay Times

A novel excimer laser process has been developed for generating cylindrical via holes with an aspect ratio of about one. The fabrication process is being successfully run on a production line for a highly miniaturized printed circuit board used for the multichip module in the new Siemens 7500 H 90 mainframe computer. The process is outstanding in terms of reliability and reproducibility. To the best of our knowledge, this is the first that that excimer lasers have been put into large-scale use in an industrial environment.Since signal delay times for chips have decreased much more rapidly than delay times for packaging, the computing speed of high-speed computers is restricted by the packaging techniques used. Therefore, further development of packaging technology became a prime objective for those developing high-performance computers. Packaging delay times had to be reduced drastically to keep up with increasingly shorter chip delay times. This, in effect, meant that a greater packaging density had to be implemented.A novel planar packaging technique has lead to considerable progress in solving this problem. This technique has been described in detail elsewhere. A key component in this technology is a multichip module, which can take in each of 16 areas, either an LSI module with 320 leads or 9 MSI modules with 52 leads as “bare” ICs. This means that a micro-wiring printed circuit board of this kind can accomodate between 16 (LSI) and 144 (MSI) chips. This article describes how these printed circuit boards are manufactured.As the specifications (Table I) show, blind vias 80 μm in diameter at a pitch of 0.5 mm have to be made in a 16-layer printed circuit board. It is intended that these blind vias will provide the through-contact for neighboring layers. The excimer laser plays a major role in this process.

scholarly journals Toward a fully integrated automotive radar system-on-chip in 22 nm FD-SOI CMOS

2021 ◽  
pp. 1-9
Author(s):  
Philipp Ritter
Keyword(s):  
Millimeter Wave ◽  
Flip Chip ◽  
Printed Circuit Board ◽  
Digital Signal ◽  
Cmos Technology ◽  
Radar System ◽  
Circuit Board ◽  
Processing Unit ◽  
Automotive Radar ◽  
On Chip

Abstract Next-generation automotive radar sensors are increasingly becoming sensitive to cost and size, which will leverage monolithically integrated radar system-on-Chips (SoC). This article discusses the challenges and the opportunities of the integration of the millimeter-wave frontend along with the digital backend. A 76–81 GHz radar SoC is presented as an evaluation vehicle for an automotive, fully depleted silicon-over-insulator 22 nm CMOS technology. It features a digitally controlled oscillator, 2-millimeter-wave transmit channels and receive channels, an analog base-band with analog-to-digital conversion as well as a digital signal processing unit with on-chip memory. The radar SoC evaluation chip is packaged and flip-chip mounted to a high frequency printed circuit board for functional demonstration and performance evaluation.

scholarly journals Design and Implementation of SOC-Based Noncontact-Type Level Sensing for Conductive and Nonconductive Liquids

2021 ◽  
Vol 2021 ◽  
pp. 1-12
Author(s):  
J. L. Mazher Iqbal ◽  
Munagapati Siva Kishore ◽  
Arulkumaran Ganeshan ◽  
G. Narayan
Keyword(s):  
Printed Circuit Board ◽  
System On Chip ◽  
Circuit Board ◽  
Sensor Technology ◽  
Electromechanical Systems ◽  
Printed Circuit ◽  
Design And Implementation ◽  
Hardware System ◽  
On Chip

In contrast to the existing electromechanical systems, the noncontact-type capacitive measurement allows for a chemically and mechanically isolated, continuous, and inherently wear-free measurement. Integration of the sensor directly into the container’s wall offers considerable savings potential because of miniaturization and installation efforts. This paper presents the implementation of noncontact (NC)-type level sensing techniques utilizing the Programmable System on Chip (PSoC). The hardware system developed based on the PSoC microcontroller is interfaced with capacitive-based printed circuit board (PCB) strip. The designer has the choice of placing the sensors directly on the container or close to it. This sensor technology can measure both the conductive and nonconductive liquids with equal accuracy.

Design of Equivalent Sampling Based on Printed Circuit Board Suited for Power Communication System

2013 ◽  
Vol 333-335 ◽  
pp. 465-471
Author(s):  
Chuan Liu ◽  
Zhi Chao Huang ◽  
Peng Wu ◽  
Lei Chen ◽  
Wei Wang
Keyword(s):  
Time Delay ◽  
Communication System ◽  
High Speed ◽  
Printed Circuit Board ◽  
Circuit Board ◽  
Transmission Time ◽  
Clock Signal ◽  
Signal Delay ◽  
Printed Circuit ◽  
Sequential Logic

Many applications in Power communication system have a demand of adjustable transmission time delay of high-speed signal. In sequential logic circuit, the control of transmission time delay of high-speed signal can effectively improve the accuracy of clock sampling, as a result, satisfy the constraints between clock signal and periodic data. A method of equivalent sampling based on printed circuit board (PCB) is provided in the article, it realizes equivalent sampling of the data by fixing a group of clock signal delay, thus, increase the accuracy of sampling.

Superconducting Multilayer High-Density Flexible Printed Circuit Board for Very High Thermal Resistance Interconnections

2018 ◽  
Vol 193 (3-4) ◽  
pp. 578-584 ◽  
Author(s):  
Xavier de la Broïse ◽  
Alain Le Coguie ◽  
Jean-Luc Sauvageot ◽  
Claude Pigot ◽  
Xavier Coppolani ◽  
...  
Keyword(s):  
Thermal Resistance ◽  
Printed Circuit Board ◽  
High Density ◽  
Circuit Board ◽  
Printed Circuit ◽  
Flexible Printed Circuit ◽  
High Thermal Resistance ◽  
Very High

Pretreatment of Blind Via Holes before Ni/Au and Cu Plating Applied with Atmospheric Pressure Plasma Jet

2005 ◽  
Vol 2 (3) ◽  
pp. 189-196 ◽  
Author(s):  
Yasushi Sawada ◽  
Keiichi Yamazaki ◽  
Noriyuki Taguchi ◽  
Tetsuji Shibata
Keyword(s):  
Atmospheric Pressure ◽  
Printed Circuit Board ◽  
Formation Rate ◽  
Plasma Processing ◽  
Atmospheric Pressure Plasma ◽  
Plasma Jet ◽  
Circuit Board ◽  
Bottom Surface ◽  
Printed Circuit ◽  
Via Holes

The effectiveness of atmospheric pressure (AP) plasma preprocessing before Ni/Au or Cu plating has been examined by applying it to a build-up printed circuit board (FR-4 grade) and polyimide-based flexible circuit film, both with blind via-holes (BVHs). The AP plasma applied with a dielectric barrier discharge is generated inside a 56 mm wide quartz vessel by an RF power generator using Ar-O2 gas mixture. One side of the vessel is open and the plasma jet is blown on the sample substrate transported 5 mm downward from the outlet of the vessel. The deposit failure rate of Ni/Au electroless deposit to 50 μm-diameter BVHs formed on a photo resist on the printed circuit board is 12.5% without preprocessing but is decreased to 0% after applying the AP plasma processing. As for 50 μm-diameter BVHs formed with a YAG laser on a polyimide-based flexible circuit film, the bump formation using electrolytic copper plating fails without preprocessing, but a 100% bump formation rate is achieved after applying AP plasma processing. It is presumed that the AP plasma processing improves the wetting property of the BVH walls and allows the plating solution to uniformly cover the entire wall surfaces without generating bubbles. The removal of organic substances attached to the BVH bottom surface also helps to improve the adherence of metal plating.

Optimized High Power GaN Transistors

2015 ◽  
Vol 2015 (HiTEN) ◽  
pp. 000195-000199
Author(s):  
J. Roberts ◽  
A. Mizan ◽  
L. Yushyna
Keyword(s):  
High Speed ◽  
Figure Of Merit ◽  
Printed Circuit Board ◽  
Heat Removal ◽  
Vital Role ◽  
Circuit Board ◽  
Die Structure ◽  
Power Switches ◽  
On Chip ◽  
Very High

GaN transistors intended for use at 600–900 V and that are capable of providing of 30–100 A are being introduced this year. These devices have a substantially better switching Figure-of-Merit (FOM) than silicon power switches. Rapid market acceptance is expected leading to compound annual growth rates of 85 %. However these devices present new packaging challenges. Their high speed combined with the very high current being switched demands that very low inductance packaging must be combined with highly controlled drive circuitry. While convention, and the usually vertical power device die structure, has largely determined power transistor package formats in the past, the lateral nature of the today GaN devices requires the use of new package types. The new packages have to operate at high temperatures while providing effective heat removal, low inductance, and low series resistance. Because GaN devices are lateral they require the package metal tracks to be integrated within the on-chip tracks to carry the current away from the thin on-chip metal tracks. The new GaN devices are available in two formats: one for use in embedded modular assemblies and the other for use mounted upon conventional circuit board systems. The package intended for discrete printed circuit board (PCB) assemblies has a top side cooling option that simplifies the thermal interface to the heat sink. The paper describes the die layout including the added copper tracks. The corresponding package elements that interface directly with the surface of the die play a vital role in terms of the current handling. They also provide the interface to the external busbars that allow the package to be mounted within, or on PCB. The assembly has been subject to extensive thermal analysis and the performance of a 30 A, 650 V transistor is described.

The Die Embedded and RDL structure on the high density substrate (i-THOP®) for mobile application

2016 ◽  
Vol 2016 (1) ◽  
pp. 000001-000006
Author(s):  
Masahiro Kyozuka ◽  
Tatsuro Yoshida ◽  
Noriyoshi Shimizu ◽  
Koichi Tanaka ◽  
Tetsuya Koyama
Keyword(s):  
Mobile Devices ◽  
Manufacturing Process ◽  
Printed Circuit Board ◽  
Semiconductor Device ◽  
Current Trend ◽  
High Density ◽  
Circuit Board ◽  
Fine Pitch ◽  
Package Size ◽  
Proper Material

Abstract The current trend in the electronics industry is one of increased computing performance, combined with a seemingly unending demand for portability and increased miniaturization; this is especially evident in the significant changes to the semiconductor device. To sustain the performance-improvement trend without increasing total cost, the partitioning of single die into a multi-chip architecture is widely studied in industry. These partitioned chips are then integrated into a single system-in-package (SiP). However, partitioning a single die into multiple split die causes two major challenges. The first is that it creates the need for very high density die to die interconnection. This interconnection is needed to provide enough routing density between the multiple die. Based on design studies, it believes that 2μm line and 2μm space is required in the package substrate. The second challenge is created by the increase in the overall die size. After partitioning the single die, each resulting smaller die must have its own I/O circuits, and effectively increases the total die area. This increase is a penalty, as mobile devices have a limited package size. When comparing a conventional package on package (PoP), the SiP requires a higher pin count with a finer pitch connection between the die and the memory. This finer pitch is needed to have enough I/Os, but within a limited package size to support mobile devices. To overcome these challenges, the structure of i-THOP® with POP pad, named “i-THOP® with Die embedded +ReDestribution Layer(RDL) structure”, has been developed. Herein, i-THOP® (integrated Thin film High density Organic Package) is a type of high-density substrate A key aspect to development of Die embedded +RDL is forming the multiple redistribution layers (RDL) over die and the fine pitch via connection. To achieve this, the proper material set was selected based on stress simulations and basic experiments. Regarding the manufacturing process, a conventional printed-circuit board (PCB) production line was used to minimize production cost. This article reports the manufacturing process and characteristics of the structure.

Two-Level Nonlinear Mixed Discrete-Continuous Optimization-Based Design: An Application to Printed Circuit Board Assemblies

1992 ◽  
Vol 114 (4) ◽  
pp. 425-435 ◽  
Author(s):  
S. Praharaj ◽  
S. Azarm
Keyword(s):  
Large Scale ◽  
Printed Circuit Board ◽  
Continuous Optimization ◽  
The Other ◽  
Circuit Board ◽  
Continuous Variables ◽  
Discrete Variables ◽  
Printed Circuit ◽  
Monotonicity Analysis ◽  
Optimization Based Design

In this paper, a new approach for optimization-based design of nonlinearly mixed discrete-continuous problems has been developed. The approach is based on a two-level decomposition strategy in which the entire domain of variables is partitioned into two levels, one involving the continuous variables and the other involving the discrete variables. Variables in one level are optimized for fixed values of the variable from the other level. A modified penalty function is formed, based on monotonicity analysis, to solve for the discrete variables, and a conventional optimization method is used to solve for the continuous variables. To improve the computational effectiveness of the approach, a constrained derivative relationship is also adopted. The performance of the entire algorithm is then demonstrated through an example involving a simplified model for printed circuit board assemblies. The objective in the example is to maximize assembly reliability by: (1) adding redundant components to the boards, and (2) optimally distributing allocated mass flow to the individual channels of the circuit boards. Number of variables in the example is then varied to investigate the effectiveness and potential of the approach for large-scale problems.

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