Stress in Titanium Disilicide Layers, During and After Formation.

1988 ◽  
Vol 130 ◽  
Author(s):  
J. F. Jongste ◽  
F. E. Prins ◽  
G. C. A. M. Janssen ◽  
S. Radelaar
Keyword(s):  
Silicon Substrate ◽  
Semiconductor Device ◽  
Linear Thermal Expansion ◽  
Deposition Process ◽  
Device Fabrication ◽  
Titanium Disilicide ◽  
Titanium Layer ◽  
Thermal Expansion Coefficients ◽  
The Difference ◽  
Interconnect Lines

AbstractDuring and after formation of a thin layer of titanium disilicide (TiSi2) on a silicon substrate stress is caused in several ways: Intrinsic stresses are due to the deposition process or to phase transformations and grain growth of the deposited material. Extrinsic stresses are caused by thermal effects: the difference in linear thermal expansion coefficients of the layer and the substrate respectively. Problems related to stresses can occur in semiconductor device fabrication. Stresses can deteriorate gate oxides in MOSFETs and can cause cracks in interconnect lines. Also, focusing problems in lithographic steps can occur because of wafer warpage. In this paper some examples of the different types of stress that can occur are shown and discussed. Both multilayer and self aligned Ti-Si samples have been studied: The advantage of the use of Ti-Si multilayers to produce TiSi2 is that diffusion has to proceed only over a short distance i.e., the multilayer period. So the annealing time can be short. In the self aligned silicidation process, where a layer of a titanium layer on top of a silicon substrate is annealed, the diffusion length is equal to the thickness of the Ti layer. Because longer annealing times are needed, the latter type is used to monitor stress during formation.

Rutherford backscattering & TEM studies of nitrogen, oxygen & argon incorporation in sputter-deposited titanium nitride films

1987 ◽  
Vol 45 ◽  
pp. 250-251
Author(s):  
J.M. Brown ◽  
F.A. Baiocchi ◽  
D.S. Williams ◽  
R.C. Beairsto ◽  
R.V. Knoell ◽  
...  
Keyword(s):  
Titanium Nitride ◽  
Semiconductor Device ◽  
Deposition Process ◽  
Argon Atmosphere ◽  
Device Fabrication ◽  
Rutherford Backscattering ◽  
Substrate Bias ◽  
Target Power ◽  
Sputter Deposited ◽  
And Diffusion

Titanium nitride films are incorporated into semiconductor device fabrication to form both contacts and diffusion barriers. These films are often deposited by means of reactive sputtering of a titanium nitride target in an argon atmosphere. During the course of the deposition process, gaseous components may be incorporated into the films resulting in changes in their physical and electrical properties.The stress and resistivity of titanium nitride films have been measured as a function of several processing variables: i) target power, ii) substrate bias, iii) pressure and iv) N2/Ar ratio. The concentration of oxygen, nitrogen and argon and their distribution throughout the films were measured using Rutherford Backscattering Spectroscopy of 2.12MeV helium ions generated in a General Ionex 1.7MV accelerator.

scholarly journals New Approaches in Flexible Organic Field-Effect Transistors (FETs) Using InClPc

Materials ◽  
2019 ◽  
Vol 12 (10) ◽  
pp. 1712 ◽  
Author(s):  
María Elena Sánchez-Vergara ◽  
Leon Hamui ◽  
Sergio González Habib
Keyword(s):  
Optical Properties ◽  
Indium Tin Oxide ◽  
Field Effect ◽  
Semiconductor Device ◽  
Field Effect Transistors ◽  
Low Cost ◽  
Deposition Process ◽  
Device Fabrication ◽  
Organic Field Effect Transistors ◽  
Potential Applications

Organic semiconductor materials have been the center of attention because they are scalable, low-cost for device fabrication, and they have good optical properties and mechanical flexibility, which encourages their research. Organic field-effect transistors (OFETs) have potential applications, specifically in flexible and low-cost electronics such as portable and wearable technologies. In this work we report the fabrication of an InClPc base flexible bottom-gate/top-contact OFET sandwich, configured by the high-evaporation vacuum technique. The gate substrate consisted of a bilayer poly(ethylene terephthalate) (PET) and indium–tin oxide (ITO) with nylon 11/Al2O3. The device was characterized by different techniques to determine chemical stability, absorbance, transmittance, bandgap, optical properties, and electrical characteristics in order to determine its structure and operational properties. IR spectroscopy verified that the thin films that integrated the device did not suffer degradation during the deposition process, and there were no impurities that affected the charge mobility in the OFET. Also, the InClPc semiconductor IR fingerprint was present on the deposited device. Surface analysis showed evidence of a nonhomogeneous film and also a cluster deposition process of the InClPc. Using the Tauc model, the device calculated indirect bandgap transitions of approximately 1.67 eV. The device’s field effect mobility had a value of 36.2 cm2 V−1 s−1, which was superior to mobility values obtained for commonly manufactured OFETs and increased its potential to be used in flexible organic electronics. Also, a subthreshold swing of 80.64 mV/dec was achieved and was adequate for this kind of organic-based semiconductor device. Therefore, semiconductor functionality is maintained at different gate voltages and is transferred accurately to the film, which makes these flexible OFETs a good candidate for electronic applications.

All Wet Photoresist Strip by Solvent Aerosol Spray

2009 ◽  
Vol 145-146 ◽  
pp. 285-288 ◽  
Author(s):  
Masayuki Wada ◽  
Kenichi Sano ◽  
James Snow ◽  
Rita Vos ◽  
L.H.A. Leunissens ◽  
...  
Keyword(s):  
Silicon Substrate ◽  
High Velocity ◽  
Semiconductor Device ◽  
Device Fabrication ◽  
Metal Gates ◽  
Aerosol Spray ◽  
High K ◽  
Pre Treatment

The introduction of metal gates and high-k dielectrics in FEOL and porous ULK dielectrics in BEOL presents severe issues [1] and leads to the requirement of new chemistries and processes. A major challenge in cleaning is the removal of photoresist (PR) in both FEOL and BEOL. In current semiconductor device fabrication flow, the photoresist strip process in FEOL is mostly achieved by applying a sequence of plasma ashing followed by a wet-clean step with sulfuric-peroxide mixture (SPM). But in general, ashing leads to strong oxidation or etching of silicon substrate. Hence, several approaches for ashless PR strip have been reported, such as hot SPM [2] and the combination of a pre-treatment using high velocity CO2 aerosol [3].

A Study on Metal-Ceramic Thermal Expansion Compatibility

2014 ◽  
Vol 216 ◽  
pp. 85-90
Author(s):  
Marian Miculescu ◽  
Mihai Branzei ◽  
Florin Miculescu ◽  
Daniela Meghea ◽  
Marin Bane
Keyword(s):  
Thermal Expansion ◽  
Bonding Strength ◽  
Linear Thermal Expansion ◽  
Metal Bonding ◽  
Thermal Expansion Coefficients ◽  
Metal Ceramic ◽  
Thermal Compatibility ◽  
Expansion Coefficients ◽  
The Difference ◽  
Dental Applications

Push rod method for determining linear thermal expansion using vertical differential dilatometer was used in the study of the thermal compatibility of metal-ceramic systems for dental applications. The purpose of this study consisted in evaluating the effectiveness of dental coating by determining the ceramic metal bonding strength of metal-ceramic couples (Ni-Cr and Co-Cr alloy coated with dental ceramic) and correlation with the difference of linear thermal expansion coefficients of metals and ceramics.

Correlation of Cleaning Conditions and Wafer Out-Gassing

2014 ◽  
Vol 219 ◽  
pp. 260-264
Author(s):  
Sok Hyung Han ◽  
Tae Ho Hwang ◽  
Si Chul Kim ◽  
Seung Ha Park ◽  
Byung Sul Ryu
Keyword(s):  
Deposition Process ◽  
Device Fabrication ◽  
Film Deposition ◽  
Fabrication Process ◽  
Single Type ◽  
Thickness Change ◽  
Layer Deposition ◽  
Dispersion Problem ◽  
Deposition Thickness ◽  
The Difference

To remove the oxide layer, BOE (Buffered Oxide Etchant) is widely used solution in semiconductor fabrication process. When using the BOE solution in single type equipment, NH3 ions are created by the chemical reaction. Because BOE is a mixture solution of NH4F and HF. And created NH3 ions make some problems during device fabrication process. As the device is shrinked, NH3 ion control in process chamber becomes more important. We studied the thickness change caused by NH3 ion.When backside cleaning process using the BOE solution, surface of backside was changed. And it affected the next poly layer deposition process. As a result, poly layer deposition thickness dispersion problem was occurred. We find that the difference between normal wafer and issued wafer about backside layer and fumed NH3 ion is main factor of this problem. In this paper, we will explain the cause of poly thickness dispersion issue that occurred at poly film deposition and analyze measurement of cleaning conditions by NH3 out-gassing.Key Words: Poly deposition thickness, NH3+ ion, BOE(Buffered Oxide Etchant),APM(Ammonium Peroxide Mixture), Out-gassing

Effect of Texture on Hillock Formation in Aluminum Films

2002 ◽  
Vol 721 ◽  
Author(s):  
T. Muppidi ◽  
Y. Kusama ◽  
D.P. Field
Keyword(s):  
Void Formation ◽  
Orientation Imaging Microscopy ◽  
Substrate Material ◽  
Boundary Structure ◽  
Aluminum Films ◽  
Thermal Expansion Coefficients ◽  
Grain Boundary Structure ◽  
The Difference ◽  
Interconnect Lines ◽  
Scanning Electron

AbstractStress voiding describes a phenomenon in thin interconnect lines where hillocks and voids are formed during thermal cycling due to the stresses caused by the difference in the thermal expansion coefficients of metal used in the interconnect lines and the substrate material. The effect of texture on stress voiding in aluminum interconnects is investigated using orientation imaging microscopy (OIM© ) and scanning electron microscopy. Aluminum films were deposited by PVD deposition onto sublayers of Ti and Ti plus TiN and were analyzed for crystallographic texture and grain boundary structure using OIM©. These films were later annealed at 400°C for 1 hour and cooled. The specimens were examined for the presence of hillocks and voids using a scanning electron microscope. The results show strongly textured (111) films are more resistant to hillock and void formation.

Defects in β-SiC thin films grown on α-SiC substrates

1988 ◽  
Vol 46 ◽  
pp. 568-569
Author(s):  
Karren L. More
Keyword(s):  
Thin Films ◽  
Semiconductor Device ◽  
Lattice Mismatch ◽  
Chemical Vapor ◽  
Substrate Material ◽  
Growth Interface ◽  
Si Substrates ◽  
Thermal Expansion Coefficients ◽  
Device Applications ◽  
Expansion Coefficients

Beta-SiC is an ideal candidate material for use in semiconductor device applications. Currently, monocrystalline β-SiC thin films are epitaxially grown on {100} Si substrates by chemical vapor deposition (CVD). These films, however, contain a high density of defects such as stacking faults, microtwins, and antiphase boundaries (APBs) as a result of the 20% lattice mismatch across the growth interface and an 8% difference in thermal expansion coefficients between Si and SiC. An ideal substrate material for the growth of β-SiC is α-SiC. Unfortunately, high purity, bulk α-SiC single crystals are very difficult to grow. The major source of SiC suitable for use as a substrate material is the random growth of {0001} 6H α-SiC crystals in an Acheson furnace used to make SiC grit for abrasive applications. To prepare clean, atomically smooth surfaces, the substrates are oxidized at 1473 K in flowing 02 for 1.5 h which removes ∽50 nm of the as-grown surface. The natural {0001} surface can terminate as either a Si (0001) layer or as a C (0001) layer.

Tem analysis of multiple-energy arsenic implanted and Rta'd silicon

1987 ◽  
Vol 45 ◽  
pp. 246-247
Author(s):  
R.A. Herring
Keyword(s):  
Device Fabrication ◽  
High Concentration ◽  
Tem Analysis ◽  
Defect Clusters ◽  
High Fluences ◽  
Small Defect ◽  
Before And After ◽  
The Matrix ◽  
The Difference ◽  
Factor Type

Rapid thermal annealing (RTA) of ion-implanted Si is important for device fabrication. The defect structures of 2.5, 4.0, and 6.0 MeV As-implanted silicon irradiated to fluences of 2E14, 4E14, and 6E14, respectively, have been analyzed by electron diffraction both before and after RTA at 1100°C for 10 seconds. At such high fluences and energies the implanted As ions change the Si from crystalline to amorphous. Three distinct amorphous regions emerge due to the three implantation energies used (Fig. 1). The amorphous regions are separated from each other by crystalline Si (marked L1, L2, and L3 in Fig. 1) which contains a high concentration of small defect clusters. The small defect clusters were similar to what had been determined earlier as being amorphous zones since their contrast was principally of the structure-factor type that arises due to the difference in extinction distance between the matrix and damage regions.

Behavior of contact-silicided TFSOI gate structures

1994 ◽  
Vol 52 ◽  
pp. 860-861
Author(s):  
N. David Theodore ◽  
Juergen Foerstner ◽  
Peter Fejes
Keyword(s):  
Semiconductor Device ◽  
Series Resistance ◽  
Field Effect Transistors ◽  
Silicon Layer ◽  
Device Fabrication ◽  
Silicon On Insulator ◽  
Continuous Layer ◽  
Buried Oxide ◽  
Device Structures ◽  
Thin Silicon

As semiconductor device dimensions shrink and packing-densities rise, issues of parasitic capacitance and circuit speed become increasingly important. The use of thin-film silicon-on-insulator (TFSOI) substrates for device fabrication is being explored in order to increase switching speeds. One version of TFSOI being explored for device fabrication is SIMOX (Silicon-separation by Implanted OXygen).A buried oxide layer is created by highdose oxygen implantation into silicon wafers followed by annealing to cause coalescence of oxide regions into a continuous layer. A thin silicon layer remains above the buried oxide (~220 nm Si after additional thinning). Device structures can now be fabricated upon this thin silicon layer.Current fabrication of metal-oxidesemiconductor field-effect transistors (MOSFETs) requires formation of a polysilicon/oxide gate between source and drain regions. Contact to the source/drain and gate regions is typically made by use of TiSi2 layers followedby Al(Cu) metal lines. TiSi2 has a relatively low contact resistance and reduces the series resistance of both source/drain as well as gate regions

Influence of Magnetoelastic Anisotropy on Properties of Nanostructured Microwires

2013 ◽  
Vol 646 ◽  
pp. 59-66 ◽  
Author(s):  
Arcady Zhukov ◽  
Margarita Churyukanova ◽  
Lorena Gonzalez-Legarreta ◽  
Ahmed Talaat ◽  
Valentina Zhukova ◽  
...  
Keyword(s):  
Heat Capacity ◽  
Hysteresis Loops ◽  
Magnetic Behaviour ◽  
Soft Magnetic ◽  
Magnetoelastic Anisotropy ◽  
Thermal Expansion Coefficients ◽  
Magnetoelastic Energy ◽  
Expansion Coefficients ◽  
The Difference ◽  
Magneto Resistance

We studied the effect ofthe magnetoelastic ansitropy on properties of nanostructured glass-coated microwires with soft magnetic behaviour (Finemet-type microwires of Fe70.8Cu1Nb3.1Si14.5B10.6, Fe71.8Cu1Nb3.1Si15B9.1 and Fe73.8Cu1Nb3.1Si13B9.1 compositions) and with granular structure (Cu based Co-Cu microwires). The magnetoelastic energy originated from the difference in thermal expansion coefficients of the glass and metallic alloy during the microwires fabrication, affected the hysteresis loops, coercivity and heat capacity of Finemet-type microwires. Hysteresis loops of all as-prepared microwires showed rectangular shape, typical for Fe-rich microwires. As expected, coercivity, HC, of as-prepared microwires increases with decreasing of the ratio ρ defined as the ratio between the metallic nucleus diameter, d to total microwire diameter, D. On the other hand we observed change of heat capacity in microwires with different ratio ρ. In the case of Co-Cu microwires ρ- ratio affected the structure and the giant magneto-resistance of obtained microwires.

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