Growth and Characterization of Multilayered Structure of GaAs/Epi-Si/SiO2 /Si Composite

1988 ◽  
Vol 116 ◽  
Author(s):  
C.S. Yang ◽  
A. S. Yue
Keyword(s):  
Integrated Circuits ◽  
Transmission Line ◽  
High Speed ◽  
Multilayered Structure ◽  
Radiation Hardness ◽  
Silicon On Insulator ◽  
Si Substrates ◽  
Gaas Films ◽  
Line Loss

The monolithic integration of GaAs and Si devices is highly attractive for very high speed LSI and optoelectronic integrated circuits. To accomplish this, the epitaxial growth of GaAs films on Si substrates has been successfully realized. However, in the GaAs/Si structure, the conductive nature of the silicon substrate results in a severe transmission line loss [1,2]. To help solve this problem, we suggest to grow GaAs film on SOI (silicon on insulator) substrate for microwave device application. This GaAs/SOI structure will have low transmission line loss and excellent radiation hardness. In this paper, we present some cross-section SEM and TEM data and discuss the transmission line loss and radiation hardness of this multilayered structure.

Structural changes in silicon-on-insulator material during post-implantation annealing

1986 ◽  
Vol 44 ◽  
pp. 736-737
Author(s):  
C. O. Jung ◽  
S. J. Krause ◽  
S.R. Wilson
Keyword(s):  
Integrated Circuits ◽  
Oxide Layer ◽  
High Speed ◽  
Structural Changes ◽  
Device Fabrication ◽  
Silicon On Insulator ◽  
High Quality ◽  
Radiation Hardened ◽  
Post Implantation ◽  
Very High

Silicon-on-insulator (SOI) structures have excellent potential for future use in radiation hardened and high speed integrated circuits. For device fabrication in SOI material a high quality superficial Si layer above a buried oxide layer is required. Recently, Celler et al. reported that post-implantation annealing of oxygen implanted SOI at very high temperatures would eliminate virtually all defects and precipiates in the superficial Si layer. In this work we are reporting on the effect of three different post implantation annealing cycles on the structure of oxygen implanted SOI samples which were implanted under the same conditions.

Molecular Beam Epitaxial Growth and Characterization of GaAs Films on Thin Si Substrates

1998 ◽  
Vol 37 (Part 1, No. 1) ◽  
pp. 39-44 ◽  
Author(s):  
Kenzo Maehashi ◽  
Hisao Nakashima ◽  
Frank Bertram ◽  
Peter Veit ◽  
Jürgen Christen
Keyword(s):  
Epitaxial Growth ◽  
Molecular Beam ◽  
Si Substrates ◽  
Molecular Beam Epitaxial ◽  
Gaas Films ◽  
Molecular Beam Epitaxial Growth

Evening Panel Session (November 16, 1983) Soi Technologies for Integrated Circuits

1983 ◽  
Vol 23 ◽  
Author(s):  
John C. C. Fan ◽  
Y. Akasaka ◽  
G. W. Cullen ◽  
J. F. Gibbons ◽  
C. Hill ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
High Speed ◽  
High Density ◽  
Silicon On Insulator ◽  
Panel Session ◽  
Near Term

There are a number of viable approaches to silicon-on-insulator (SOI) technologies, and the panel session has assembled a number of leaders in the SOI community for their views of “SOI Technologies for Integrated Circuits.” Their viewpoints, shown in tabulated form, were presented for general discussion in the session which was attended by about 150 people. Although SOI technologies are useful for many applications, most of the panelists agreed that the most appropriate near-term applications are for high-speed, high-density integrated circuits. Various SOI technologies, including silicon-on-sapphire (SOS), are currently in the running, but the majority of the panelists felt that for SOI technologies to be widely adopted, SOI must be available as a proven manufactured product within two to three years.

Fabrication of Thin-Film Transistors Using PECVD-Grown Carbon Nanotubes and Their Application to Integrated Circuits

2012 ◽  
Vol 1451 ◽  
pp. 159-168
Author(s):  
Takashi Mizutani ◽  
Shigeru Kishimoto
Keyword(s):  
Integrated Circuits ◽  
Scanning Probe Microscopy ◽  
High Speed ◽  
Chemical Vapor ◽  
Ring Oscillator ◽  
Scanning Probe ◽  
Preferential Growth ◽  
Current Voltage ◽  
Current Voltage Characteristics

ABSTRACTMedium scale integrated circuits with 108 CNT-TFTs have been fabricated using CNTs grown by plasma enhanced chemical vapor deposition (PECVD) which has the advantage of preferential growth of CNTs with semiconducting behavior in the FET current–voltage characteristics. High-speed operation with a switching time of 0.51 μs/gate, which is highest in the CNT-TFT integrated circuits to our knowledge, was demonstrated by a 53-stage ring oscillator. Characterization of CNT-TFTs using scanning probe microscopy has also been performed. The island-like structure in the electrical properties of the CNT network was observed even in a high-density CNT network in the subthreshold regime. This was explained by the decrease of the effective number of CNTs which contribute the electrical conduction.

Material Characterization of Epitaxial GaAs and Ge Films on (100) Si Substrates

1986 ◽  
Vol 67 ◽  
Author(s):  
M. Abdul Awal ◽  
El Hang Lee ◽  
G. L. Koos ◽  
E. Y. Chan ◽  
G. K. Celler ◽  
...  
Keyword(s):  
Material Characterization ◽  
Defect Density ◽  
Electrical Characterization ◽  
Electron Beam Evaporation ◽  
Cross Sectional ◽  
X Ray ◽  
Si Substrates ◽  
Exponential Decrease ◽  
Gaas Films

ABSTRACTWe report some results on the chemical, structural and electrical characterization of Ge and GaAs films, grown on Si (100) substrates by electron-beam evaporation and MOCVD, respectively. Good quality Ge films have been obtained at 700°C substrate temperature at a growth rate of 5 nm/sec in 5 × 10−7 torr. Similarly, good GaAs films were obtained at 650°C and at 0.3 nm/sec. RBS data for GaAs films (1.1 μm) show Xmin approaching 3.5%, and Ge films (1.5 μm) around 3.6%. Photoluminescence of the same films show peaks around 852 nm with FWHM of 14 meV. Cross-sectional TEM and etching show a near-exponential decrease in defect density away from the Ge/Si interface. Detailed characterization results of the S-R, I-V, C-V, and X-ray studies are also described.

scholarly journals The Influence that Via Structure and Its Near Wirings Give to Transmission Line Loss in High-Speed Transmission PCB

2017 ◽  
Vol 20 (4) ◽  
pp. 196-202
Author(s):  
Kaoru Sugimoto ◽  
Kenichi Kawai ◽  
Hiroyuki Adachi ◽  
Daisuke Mizutani ◽  
Tomoyuki Akahoshi ◽  
...  
Keyword(s):  
Transmission Line ◽  
High Speed ◽  
Line Loss

Precipitation in silicon-on-insulator material during high- temperature annealing

1987 ◽  
Vol 45 ◽  
pp. 254-255
Author(s):  
S. J. Krause ◽  
C. O. Jung ◽  
S.R. Wilson
Keyword(s):  
High Temperature ◽  
Integrated Circuits ◽  
Annealing Time ◽  
High Speed ◽  
Device Fabrication ◽  
Silicon On Insulator ◽  
Precipitate Size ◽  
High Dose ◽  
High Temperature Annealing ◽  
Implantation Energy

Silicon-on-insulator (SOI) structure by high dose oxygen implantation (SIMOX) has excellent potential for use in radiation hardened and high speed integrated circuits. Device fabrication in SIMOX requires a high quality superficial Si layer above the buried oxide layer. Previously we reported on the effect of heater temperature, background doping, and annealing cycle on precipitate size, density, and location in the superficial Si layer. Precipitates were not eliminated with our processing conditions, but various authors have recently reported that high temperature annealing of SIMOX, from 1250°C to 1405°C, eliminates virtually all precipitates in the superficial Si layer. However, in those studies there were significant differences in implantation energy and dose and also annealing time and temperature. Here we are reporting on the effect of annealing time and temperature on the formation and changes in precipitates.

Transmission Line Design for Testing High-Speed Integrated Circuits with Differential Signals

2019 ◽  
Author(s):  
Nandish Bharat Thaker ◽  
Rakesh Ashok ◽  
Sarath Manikandan ◽  
Nandakumar Nambath ◽  
Shalabh Gupta
Keyword(s):  
Integrated Circuits ◽  
Transmission Line ◽  
High Speed ◽  
Line Design

Silicon-on-lnsulator Technology

MRS Bulletin ◽  
1998 ◽  
Vol 23 (12) ◽  
pp. 13-15 ◽  
Author(s):  
Jean-Pierre Colinge ◽  
Robert W. Bower
Keyword(s):  
Integrated Circuits ◽  
High Speed ◽  
Low Voltage ◽  
Silicon On Insulator ◽  
Cellular Phones ◽  
Long Time ◽  
Circuit Development ◽  
Materials Used ◽  
The 1960S ◽  
Soi Technology

Silicon-on-lnsulator (SOI) technology has been around since the 1960s when so-called silicon on sapphire (SOS) was first introduced. Silicon on sapphire has been used for many years for the fabrication of spaceborne and high-speed integrated circuits. It is still used in the fabrication of radio-frequency circuits.More recent SOI materials involve only silicon and silicon dioxide—the two most common materials used in the fabrication of integrated circuits—as opposed to SOS, which requires the use of an alumina substrate.Silicon-on-insulator technology has been used for a long time in niche applications such as spacecraft electronics and devices operating in a hightemperature or radiative environment. Recently however much attention has been paid to SOI technology because it is extremely suitable for the fabrication of low-voltage integrated circuits. Such circuits are in high demand for all kinds of portable systems, ranging from cellular phones to laptop computers. In August of 1998, IBM, Sharp, and other semiconductor manufacturers announced the development of SOI chips for high-speed computing and telecommunication con-sumer electronics. Most major semiconductor companies are putting considerable effort into SOI-circuit development for mainstream low-power applications.

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