Efficacy of Damage Annealing in Advanced Ultra-Shallow Junction Processing

2008 ◽  
Vol 1070 ◽  
Author(s):  
Paul J Timans ◽  
Yao Zhi Hu ◽  
Jeff Gelpey ◽  
Steve McCoy ◽  
Wilfried Lerch ◽  
...  
Keyword(s):  
Leakage Current ◽  
Crystalline Silicon ◽  
Solid Phase ◽  
Rapid Assessment ◽  
Critical Factor ◽  
Defect Annealing ◽  
Residual Damage ◽  
B Doping ◽  
Low Thermal Budget ◽  
Spike Annealing

ABSTRACTLow thermal budget annealing approaches, such as millisecond annealing or solid-phase epitaxy (SPE) of amorphized silicon, electrically activate implanted dopants while minimizing diffusion. However, it is also important to anneal damage to the crystal lattice in order to minimize junction leakage. Annealing experiments were performed on low-energy B implants into both crystalline silicon and into wafers pre-amorphized by Ge implantation. Some wafers also received As implants for halo-style doping, and in some cases the halo implants were pre-annealed at 1050°C before the B-doping. The B-implants were annealed by either SPE at 650°C, spike annealing at 1050°C, or by millisecond annealing with flash-assisted RTP™ (fRTP™) at temperatures between 1250°C and 1350°C. Residual damage was characterized by photoluminescence and non-contact junction leakage current measurements, which permit rapid assessment of damage removal efficacy. Damage from the heavy ions used for the halo and pre-amorphization implants dominates the defect annealing behaviour. The halo doping is the critical factor in determining junction leakage current. Millisecond annealing at high temperatures helps to minimize residual damage while limiting diffusion.

Formation of Nanocrystalline Silicon in Tin-Doped Amorphous Silicon Films

2020 ◽  
Vol 65 (3) ◽  
pp. 236
Author(s):  
R. M. Rudenko ◽  
O. O. Voitsihovska ◽  
V. V. Voitovych ◽  
M. M. Kras’ko ◽  
A. G. Kolosyuk ◽  
...  
Keyword(s):  
Amorphous Silicon ◽  
Crystalline Silicon ◽  
Solid Phase ◽  
Nanocrystalline Silicon ◽  
Recrystallization Temperature ◽  
Nanocrystalline Phase ◽  
Silicon Phase ◽  
Silicon Nanocrystallites ◽  
Lower Temperature ◽  
Two Stages

The process of crystalline silicon phase formation in tin-doped amorphous silicon (a-SiSn) films has been studied. The inclusions of metallic tin are shown to play a key role in the crystallization of researched a-SiSn specimens with Sn contents of 1–10 at% at temperatures of 300–500 ∘C. The crystallization process can conditionally be divided into two stages. At the first stage, the formation of metallic tin inclusions occurs in the bulk of as-precipitated films owing to the diffusion of tin atoms in the amorphous silicon matrix. At the second stage, the formation of the nanocrystalline phase of silicon occurs as a result of the motion of silicon atoms from the amorphous phase to the crystalline one through the formed metallic tin inclusions. The presence of the latter ensures the formation of silicon crystallites at a much lower temperature than the solid-phase recrystallization temperature (about 750 ∘C). A possibility for a relation to exist between the sizes of growing silicon nanocrystallites and metallic tin inclusions favoring the formation of nanocrystallites has been analyzed.

scholarly journals The Role of Electric Pressure/Stress Suppressing Pinhole Defect on Coalescence Dynamics of Electrified Droplet

Coatings ◽  
2021 ◽  
Vol 11 (5) ◽  
pp. 503
Author(s):  
Jaehyun Lee ◽  
Ehsan Esmaili ◽  
Giho Kang ◽  
Baekhoon Seong ◽  
Hosung Kang ◽  
...  
Keyword(s):  
Solid Phase ◽  
Critical Factor ◽  
Air Pressure ◽  
Conical Shape ◽  
Electric Stress ◽  
Bottom Interface ◽  
Electric Pressure ◽  
Pressure Stress ◽  
Air Film

The dimple occurs by sudden pressure inversion at the droplet’s bottom interface when a droplet collides with the same liquid-phase or different solid-phase. The air film entrapped inside the dimple is a critical factor affecting the sequential dynamics after coalescence and causing defects like the pinhole. Meanwhile, in the coalescence dynamics of an electrified droplet, the droplet’s bottom interfaces change to a conical shape, and droplet contact the substrate directly without dimple formation. In this work, the mechanism for the dimple’s suppression (interfacial change to conical shape) was studied investigating the effect of electric pressure. The electric stress acting on a droplet interface shows the nonlinear electric pressure adding to the uniform droplet pressure. This electric stress locally deforms the droplet’s bottom interface to a conical shape and consequentially enables it to overcome the air pressure beneath the droplet. The electric pressure, calculated from numerical tracking for interface and electrostatic simulation, was at least 108 times bigger than the air pressure at the center of the coalescence. This work helps toward understanding the effect of electric stress on droplet coalescence and in the optimization of conditions in solution-based techniques like printing and coating.

Optical Waveguide Formation by Ion Implantation of Ti or Ag

1988 ◽  
Vol 100 ◽  
Author(s):  
D. B. Poker ◽  
D. K. Thomas
Keyword(s):  
Ion Implantation ◽  
Concentration Profile ◽  
Optical Waveguides ◽  
Annealing Temperature ◽  
Solid Phase ◽  
Effective Means ◽  
Complete Removal ◽  
Solid Phase Epitaxy ◽  
Annealing Temperatures ◽  
Residual Damage

ABSTRACTIon implantation of Ti into LINbO3 has been shown to be an effective means of producing optical waveguides, while maintaining better control over the resulting concentration profile of the dopant than can be achieved by in-diffusion. While undoped, amorphous LiNbO3 can be regrown by solid-phase epitaxy at 400°C with a regrowth velocity of 250 Å/min, the higher concentrations of Ti required to form a waveguide (∼10%) slow the regrowth considerably, so that temperatures approaching 800°C are used. Complete removal of residual damage requires annealing temperatures of 1000°C, not significantly lower than those used with in-diffusion. Solid phase epitaxy of Agimplanted LiNbO3, however, occurs at much lower temperatures. The regrowth is completed at 400°C, and annealing of all residual damage occurs at or below 800°C. Furthermore, the regrowth rate is independent of Ag concentration up to the highest dose implanted to date, 1 × 1017 Ag/cm2. The usefulness of Ag implantation for the formation of optical waveguides is limited, however, by the higher mobility of Ag at the annealing temperature, compared to Ti.

Defect Reduction and Defect Engineering in Silicon-on-Sapphire Material Using Ge Implantation

1990 ◽  
Vol 201 ◽  
Author(s):  
F. Namavar ◽  
E. Cortesi ◽  
N. M. Kalkhoran ◽  
J. M. Manke ◽  
B. L. Buchanan
Keyword(s):  
Leakage Current ◽  
Defect Density ◽  
Solid Phase ◽  
Substantial Reduction ◽  
Interface Region ◽  
Radiation Environment ◽  
Solid Phase Epitaxy ◽  
Defect Reduction ◽  
Radiation Induced

AbstractSubstantial reduction of defect density in silicon-on-sapphire (SOS) material is required to broaden its range of applications to include CMOS and bipolar devices. In recent years, solid phase epitaxy and regrowth (SPEAR) and double solid phase epitaxy (DSPE) processes were applied to SOS to reduce the density of defects in the silicon. These methods result in improved carrier mobilities, but also in increased leakage current, even before irradiation. In a radiation environment, this material has a large increase in radiation induced back channel leakage current as compared to standard wafers. In other words, the radiation hardness quality of the SOS declines when the crystalline quality of the Si near the sapphire interface is improved.In this paper, we will demonstrate that Ge implantation, rather than Si implantation normally employed in DSPE and SPEAR processes, is an efficient and more effective way to reduce the density of defects near the surface silicon region without improving the Si/sapphire interface region. Ge implantation may be used to engineer defects in the Si/sapphire interface region to eliminate back channel leakage problems.

Impact of rapid thermal annealing and hydrogenation on the doping concentration and carrier mobility in solid phase crystallized poly-Si thin films

2011 ◽  
Vol 1321 ◽  
Author(s):  
A. Kumar ◽  
P.I. Widenborg ◽  
H. Hidayat ◽  
Qiu Zixuan ◽  
A.G. Aberle
Keyword(s):  
Thin Films ◽  
Electronic Properties ◽  
Thermal Annealing ◽  
Rapid Thermal Annealing ◽  
Carrier Mobility ◽  
Crystalline Silicon ◽  
Solid Phase ◽  
Dopant Activation ◽  
Hall Effect Measurements ◽  
Probe Measurements

ABSTRACTThe effect of the rapid thermal annealing (RTA) and hydrogenation step on the electronic properties of the n+ and p+ solid phase crystallized (SPC) poly-crystalline silicon (poly-Si) thin films was investigated using Hall effect measurements and four-point-probe measurements. Both the RTA and hydrogenation step were found to affect the electronic properties of doped poly-Si thin films. The RTA step was found to have the largest impact on the dopant activation and majority carrier mobility of the p+ SPC poly-Si thin films. A very high Hall mobility of 71 cm2/Vs for n+ poly-Si and 35 cm2/Vs for p+ poly-Si at the carrier concentration of 2×1019 cm-3 and 4.5×1019 cm-3, respectively, were obtained.

scholarly journals Индий-индуцированная кристаллизация тонких пленок аморфного субоксида кремния

2020 ◽  
Vol 46 (12) ◽  
pp. 14
Author(s):  
А.О. Замчий ◽  
Е.А. Баранов ◽  
И.Е. Меркулова ◽  
Н.А. Лунев ◽  
В.А. Володин ◽  
...  
Keyword(s):  
Crystallization Temperature ◽  
Polycrystalline Silicon ◽  
Crystalline Silicon ◽  
Solid Phase ◽  
High Vacuum ◽  
Stoichiometric Coefficient ◽  
Free Standing ◽  
Solid Phase Crystallization ◽  
Silicon Suboxide ◽  
Induced Crystallization

A novel fabrication method of polycrystalline silicon by indium-induced crystallization (InIC) of amorphous silicon suboxide thin films with a stoichiometric coefficient of 0.5 (a-SiO0.5) is proposed. It was shown that the use of indium in the annealing process of a SiO0.5 allowed to decrease the crystallization temperature to 600°С which was significantly lower than the solid-phase crystallization temperature of the material - 850°С. As a result of the high-vacuum InIC of a-SiO0.5, the formation of free-standing micron-sized crystalline silicon particles took place.

Comparison of Doping of Gey Si1-y:H (y>0.95) Films Deposited by Low Frequency PECVD at High (300°C) and Low (160°C) Temperatures

2012 ◽  
Vol 1426 ◽  
pp. 295-299
Author(s):  
Ismael Cosme ◽  
Andrey Kosarev ◽  
Francisco Temoltzi Avila ◽  
Adrian Itzmoyotl
Keyword(s):  
Activation Energy ◽  
Deposition Temperature ◽  
Solid Phase ◽  
Low Frequency ◽  
General Effect ◽  
Temperature Conductivity ◽  
Room Temperature Conductivity ◽  
High Deposition Temperature ◽  
B Doping ◽  
Low Deposition Temperature

ABSTRACTIn this work we present the results of comparative study n- and p-doping of Ge:H and Ge0.96Si0.04 :H films deposited by LF PECVD at high deposition temperature (HT) Td=300°C and low deposition temperature (LT) Td=160°C. The concentration of boron and phosphorus in solid phase was measured by means of SIMS technique. Such parameters as spectral dependence of absorption coefficient, room temperature conductivity σRT and activation energy Ea for both intrinsic and doped films were obtained. The doping range studied in gas phase was for boron [B]gas= 0 to 0.15% and for phosphorus [P]gas= 0 to 0.2%. In general effect of deposition temperature on P and B doping has been demonstrated. For LT films changes of [P]gas=0.04% to 0.22% resulted in more than 2 orders increasing conductivity and reducing activation energy from Ea=0.28 to 0.16 eV. HT films in the range of [P]gas=0.04% to 0.2% demonstrated saturation of conductivity. HT films showed continuous reducing Ea with increase of [P]gas. In the case of boron doping both HT and LT films had a minimum of conductivity at certain values of [B]gas=0.05% (LT films) and 0.04% (HT films) and related maximums of activation energy Ea(max) at the same doping with Ea(max)=0.47 eV for HT and Ea(max)=0.53 eV for LT films. It suggests a compensation of electron conductivity in un-doped films for low B doping. Further raising [B]gas leads to reducing Ea and the smallest Ea=0.27 eV was obtained at [B]gas=0.18% for HT films and Ea=0.33 eV at [B]gas=0.14% for LH films.

Amorphous Silicon Crystallization For Tft Applications

1993 ◽  
Vol 321 ◽  
Author(s):  
J. Yi ◽  
R. Wallace ◽  
N. Sridhar ◽  
D. D. L. Chung ◽  
W. A. Anderson
Keyword(s):  
Thin Film ◽  
Amorphous Silicon ◽  
Leakage Current ◽  
Excimer Laser ◽  
Delay Time ◽  
Solid Phase ◽  
Laser Energy ◽  
Silicon Film ◽  
Rapid Thermal Anneal ◽  
Laser Anneal

ABSTRACTThin film hydrogenated Amorphous silicon (a-Si:H) was deposited on Molybdenum (Mo) substrates by d.c. glow discharge. We investigated the a-Si:H crystallization using four anneal techniques; nitrogen atmosphere furnace, vacuum, rapid thermal anneal (RTA), and excimer laser anneal. Anneal temperature ranged from 100 to 1200 °C. Excimer laser energy per pulse ranged from 90 to 340 M.J. Transmission electron Microscopy (TEM) revealed microstructure of crystallized Si film with grain size over 0.5 μm. X-ray diffraction (XRD) and Raman spectroscopy were employed to determine the degree of crystallization. The a-Si:H started to crystallize at temperatures over 600 °C. An 850 °C anneal reduced film resistivity to 10s (ω-cm) for intrinsic and 1 (ω-cm) for n-type. Coplanar type thin film transistors (TFT) with gate channel length of 25 μm and width of 220 μm were fabricated with various insulating layers; if sputtered SiO2, Si3N4, BaTiO3, MgO, and evaporated SiO. The first two exhibited the least leakage current. The as-grown intrinsic a-Si:H field effect mobility was around 0.03 (cmVV.s) and delay time was 5×10−7 s. The solid phase crystallized silicon film exhibited high leakage current. The delay time of an excimer laser anneal treated TFT was reduced to 2.5×10−7 s. Crystallized Si film mobility was improved to 15 (cm2 /V.s).

Flat-band Voltage Study Of Atomic-layer-Deposited Aluminum-oxide Subjected To Spike Thermal Annealing

2003 ◽  
Vol 765 ◽  
Author(s):  
V. R. Mehta ◽  
A. T. Fiory ◽  
N. M. Ravindra ◽  
M. Y. Ho ◽  
G. D. Wilk ◽  
...  
Keyword(s):  
Atomic Layer ◽  
Oxide Thickness ◽  
Atomic Diffusion ◽  
Flat Band ◽  
Gate Electrodes ◽  
Layer Deposition ◽  
Thermal Oxide ◽  
P Type ◽  
Low Thermal Budget ◽  
Spike Annealing

AbstractHigh-κ dielectrics based the oxide of Al were prepared by atomic layer deposition (ALD) on 200-mm p-type Si wafers. Films were deposited directly on clean Si or on 0.5-nm underlayers of rapid thermal oxide or oxynitrides grown in O2 and/or NO ambients. The purpose of the underlayer films is to provide a barrier for atomic diffusion from the crystal Si to the high-κ dielectric film. Deposited Al-oxide films varied in thickness from 2 to 6 nm. Post deposition anneals were used to stabilize the ALD oxides. Equivalent SiO2-oxide thickness varied from 1.0 to 3.5 nm. In situ P-doped amorphous-Si 160 nm films were deposited over the oxides to prepare heavily doped n-type gate electrodes in MOS structures. Samples were rapid thermal annealed in N2 ambient at 800°C for 30 s, or spike annealed at 950, 1000, and 1050°C (nominally zero time at peak temperature). Flat band voltages, VFB were determined from C-V measurements on dot patterns. The 800°C anneals were used as a baseline, at which the poly-Si electrodes are crystallized and acquire electrical activation while subjecting the high-κ dielectrics to a low thermal budget. Positive shifts in VFB were observed, relative to a pure SiO2 control, ranging from 0.2 to 0.8 V. Spike annealing reduces the VFB shift for ALD films deposited over underlayer films. The VFB shift and the changes with annealing temperature show systematic dependence on the nitridation of the underlayer.

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