Metallization for Very-Large-Scale Integrated Circuits

1981 ◽  
Vol 10 ◽  
Author(s):  
P. B. Ghate
Keyword(s):  
Integrated Circuits ◽  
Large Scale ◽  
Vlsi Circuits ◽  
Oxide Semiconductor ◽  
Vlsi Circuit ◽  
Chip Area ◽  
Circuit Performance ◽  
Platinum Silicide ◽  
Silicon Crystals ◽  
Device Structures

Progress in patterning technologies and computer-aided circuit designs have brought us to the threshold of very-large-scale integrated (VLSI) circuits with 100 000 or more devices to be integrated on a silicon chip. In this paper we review thin film applications in the fabrication of contacts and interconnects for VLSI circuits. Device structures suitable for both bipolar and metal/oxide/semiconductor (MOS) VLSI circuit applications tend to have shallow junction depths and contact areas (silicon-metal interfaces) in the 0.2–0.5 μm and 1–2μm2 ranges respectively; also some of the circuits require Schottky barrier diodes. Consumption of silicon in the contact windows needs to be minimized with the use of silicide layers for siliconmetal contacts. The formation and use of platinum silicide layers for bipolar applications are reviewed. Our observations indicate that the carbon and oxygen present in Czochralski-grown silicon crystals interfere in platinum silicide formationand affect the electrical characteristics of the contacts. The use of barrier layers in VLSI metallization is illustrated. The interdependence of film microstructure, electromigration-induced failures and VLSI interconnection reliability is examined. The integration of a large number of components on a VLSI chip with a single level of interconnections consumes more chip area. Long interconnection paths adversely affect circuit performance. Multilevel interconnections (conductor/insulator/conductor) offer an attractive solution to increase the packing density and circuit performance. The application of PtSi/(Ti: W)/(Al-Cu)/SiO2 /(Ti: W)/A1 film layers in the fabrication of a bipolar VLSI circuit with a minimum feature size of 1.25 μm is illustrated. As the complexity of VLSI circuits continues to grow with micron size device structures, three or more levels of interconnections compatible with shallow junctions on the substrates and complex packaging technologies are required. Areas of concern and desirable features in VLSI metallization are summarized.

Octahedral-Structured Gigantic Precipitates as the Origin of Gate-Oxide Defects in Metal-Oxide-Semiconductor Large-Scale-Integrated Circuits

1996 ◽  
Vol 35 (Part 1, No. 2B) ◽  
pp. 812-817 ◽  
Author(s):  
Manabu Itsumi ◽  
Hideo Akiya ◽  
Takemi Ueki ◽  
Masato Tomita ◽  
Masataka Yamawaki
Keyword(s):  
Integrated Circuits ◽  
Metal Oxide ◽  
Large Scale ◽  
Gate Oxide ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Oxide Defects

Excellence of Gate Oxide Integrity in Metal-Oxide-Semiconductor Large-Scale-Integrated Circuits Based onP-/P-Thin-Film Epitaxial Silicon Wafers

1997 ◽  
Vol 36 (Part 1, No. 5A) ◽  
pp. 2565-2570 ◽  
Author(s):  
Hirofumi Shimizu ◽  
Yuji Sugino ◽  
Norio Suzuki ◽  
Shogo Kiyota ◽  
Koichi Nagasawa ◽  
...  
Keyword(s):  
Thin Film ◽  
Integrated Circuits ◽  
Metal Oxide ◽  
Large Scale ◽  
Gate Oxide ◽  
Metal Oxide Semiconductor ◽  
Silicon Wafers ◽  
Oxide Semiconductor ◽  
Epitaxial Silicon ◽  
Gate Oxide Integrity

Skill Needs in VLSI Circuits

1992 ◽  
Vol 6 (1) ◽  
pp. 50-50
Author(s):  
Klaus Wölcken
Keyword(s):  
Integrated Circuits ◽  
Large Scale ◽  
Vlsi Design ◽  
Vlsi Circuits ◽  
Academic Institutions ◽  
Directorate General

The forecast need for designers of Very Large Scale Integrated Circuits is described. The article then goes on to outline the support being provided for academic institutions involved with VLSI design training by the European Commission's Directorate General XIII.

scholarly journals High-speed programmable photonic circuits in a cryogenically compatible, visible–near-infrared 200 mm CMOS architecture

2021 ◽  
Author(s):  
Mark Dong ◽  
Genevieve Clark ◽  
Andrew J. Leenheer ◽  
Matthew Zimmermann ◽  
Daniel Dominguez ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Power Consumption ◽  
High Speed ◽  
Large Scale ◽  
Near Infrared ◽  
Response Times ◽  
Photonic Integrated Circuits ◽  
Complementary Metal Oxide Semiconductor ◽  
Phase Shifters ◽  
Oxide Semiconductor

AbstractRecent advances in photonic integrated circuits have enabled a new generation of programmable Mach–Zehnder meshes (MZMs) realized by using cascaded Mach–Zehnder interferometers capable of universal linear-optical transformations on N input/output optical modes. MZMs serve critical functions in photonic quantum information processing, quantum-enhanced sensor networks, machine learning and other applications. However, MZM implementations reported to date rely on thermo-optic phase shifters, which limit applications due to slow response times and high power consumption. Here we introduce a large-scale MZM platform made in a 200 mm complementary metal–oxide–semiconductor foundry, which uses aluminium nitride piezo-optomechanical actuators coupled to silicon nitride waveguides, enabling low-loss propagation with phase modulation at greater than 100 MHz in the visible–near-infrared wavelengths. Moreover, the vanishingly low hold-power consumption of the piezo-actuators enables these photonic integrated circuits to operate at cryogenic temperatures, paving the way for a fully integrated device architecture for a range of quantum applications.

scholarly journals Design and Implementation of Ternary Logic Integrated Circuits by Using Novel Two-Dimensional Materials

2019 ◽  
Vol 9 (20) ◽  
pp. 4212 ◽  
Author(s):  
Mingqiang Huang ◽  
Xingli Wang ◽  
Guangchao Zhao ◽  
Philippe Coquet ◽  
Bengkang Tay
Keyword(s):  
Integrated Circuits ◽  
Integrated Circuit ◽  
Large Scale ◽  
2D Materials ◽  
Two Dimensional ◽  
Ternary Logic ◽  
Chip Area ◽  
Logic Devices ◽  
Ripple Carry Adder ◽  
Data Density

With the approaching end of Moore’s Law (that the number of transistors in a dense integrated circuit doubles every two years), the logic data density in modern binary digital integrated circuits can hardly be further improved due to the physical limitation. In this aspect, ternary logic (0, 1, 2) is a promising substitute to binary (0, 1) because of its higher number of logic states. In this work, we carry out a systematical study on the emerging two-dimensional (2D) materials (MoS2 and Black Phosphorus)-based ternary logic from individual ternary logic devices to large scale ternary integrated circuits. Various ternary logic devices, including the standard ternary inverter (STI), negative ternary inverter (NTI), positive ternary inverter (PTI) and especially the ternary decrement cycling inverter (DCI), have been successfully implemented using the 2D materials. Then, by taking advantage of the optimized ternary adder algorithm and the novel ternary cycling inverter, we design a novel ternary ripple-carry adder with great circuitry simplicity. Our design shows about a 50% reduction in the required number of transistors compared to the existing ternary technology. This work paves a new way for the ternary integrated circuits design, and shows potential to fulfill higher logic data density and a smaller chip area in the future.

Practical Implementation of Programmable Photonic Circuits

2020 ◽  
pp. 178-226
Author(s):  
José Capmany ◽  
Daniel Pérez
Keyword(s):  
Integrated Circuits ◽  
Large Scale ◽  
Practical Implementation ◽  
Circuit Performance ◽  
Fabrication Errors ◽  
Integration Density ◽  
Unit Cells ◽  
Complex Circuits ◽  
General Architecture ◽  
Electronic Hardware

In covering the fundamentals and ideal implementation of integrated multi-port interferometers and waveguide meshes, we saw that solutions with larger integration density of programmable unit cells enables the synthesis of more complex circuits. However, photonic integrated circuits (PICs) generally suffer from design and fabrication errors and other non-ideal working conditions, which compromises performance and scalability. In addition, PICs require the development of two additional tiers (electronic hardware and software) to allow their programmability, optimisation and (re)configuration. This chapter introduces basic practical considerations of programmable PIC design and reviews experimental demonstrations of both multi-port interferometers and waveguide mesh arrangements. It analyses the main error sources and their impact on circuit performance and investigates the most challenging evolution obstacles for very large-scale programmable PICs. It introduces an analytical method for arbitrary waveguide mesh analysis. Finally, it presents a general architecture for the control subsystem and introduces the software framework and main algorithms.

Contact Resistance and Methods for its Determination

1982 ◽  
Vol 18 ◽  
Author(s):  
S. Simon Cohen
Keyword(s):  
Integrated Circuits ◽  
Contact Resistance ◽  
Large Scale ◽  
Ohmic Contacts ◽  
Vlsi Circuits ◽  
Single Element ◽  
Large Scale Integration ◽  
Proper Definition ◽  
Definition Of ◽  
Scale Integration

The problem of low resistance ohmic contacts to silicon has been of considerable technological interest. In recent years this problem has received special attention owing to the effect of scaling in very-large-scale integration (VLSI) technology. The field of ohmic contacts to semiconductors comprises two independent parts. First there exists the material science aspect. The choice of a suitable metallization system, the proper semiconductor parameters and the method of the contact formation is not obvious. Then there is the question of the proper definition of the contact resistance and the way it is measured.Several methods for contact resistance determination have been introduced in the past. All seem to have some drawbacks that either limit their usefulness or raise doubts as to their validity in certain situations. We shall discuss the two-, three- and four-terminal resistor methods of measurement. Relevant theoretical considerations will also be included.For conventional integrated circuits with a moderate junction depth of 1–2 μm, aluminum is uniquely suited as a single-element metallization system. However, for VLSI applications it may become obsolete because of several well-defined metallurgical problems. Thus, other metallization systems have to be investigated. We shall briefly discuss some recent data on several other metallization systems. Finally, the problem of size effects on the contact resistance will be discussed. Recent experimental results suggest important clues regarding the development of alternative metallization systems for VLSI circuits and also point to revisions of estimates of achievable design rules.

An Application of Rectilinear Embedding in VLSI Placement

2013 ◽  
Vol 734-737 ◽  
pp. 2842-2845
Author(s):  
Li Yan Pan ◽  
Yan Pei Liu
Keyword(s):  
Integrated Circuits ◽  
Large Scale ◽  
Initial Step ◽  
Outerplanar Graph ◽  
Chip Area ◽  
Lagrangian Inversion ◽  
Multiple Parameters ◽  
Vlsi Physical Design ◽  
And Performance ◽  
Set Up

The VLSI (Very Large Scale Integrated Circuits) technology has developed rapidly in recent years, with a lot of advanced electric products emerging. Placement layout is regarded as the initial step in VLSI physical design. Its quality has a direct effect on the chip area and performance. The rectilinear embedding, which originates from graph theory, is widely employed in VLSI placement. In this paper, we set up a mathematical model for VLSI. Firstly, the issue of VLSI placement was converted to quadrangulation by using rectilinear embedding. Then we provided generating functions for two types of quadrangulations with graph multiple parameters. And the explicit formulae by employing Lagrangian inversion were obtained. Furthermore, we found the relation between outerplanar graph and Hamilton graph, so the counting result of Hamilton quadrangulation was derived. The quadrangulation calculation can be applied to the establishment of a computerized algorithm, which can be widely used for VLSI placement optimization.

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