A new thermoelectric concept using large area PN junctions

2013 ◽  
Vol 1543 ◽  
pp. 3-8 ◽  
Author(s):  
R. Chavez ◽  
A. Becker ◽  
V. Kessler ◽  
M. Engenhorst ◽  
N. Petermann ◽  
...  

ABSTRACTA new thermoelectric concept using large area silicon PN junctions is experimentally demonstrated. In contrast to conventional thermoelectric generators where the n-type and p-type semiconductors are connected electrically in series and thermally in parallel, we demonstrate a large area PN junction made from densified silicon nanoparticles that combines thermally induced charge generation and separation in a space charge region with the conventional Seebeck effect by applying a temperature gradient parallel to the PN junction. In the proposed concept, the electrical contacts are made at the cold side eliminating the need for contacts at the hot side allowing temperature gradients greater than 100K to be applied. The investigated PN junction devices are produced by stacking n-type and p-type nanopowder prior to a densification process. The nanoparticulate nature of the densified PN junction lowers thermal conductivity and increases the intraband traps density which we propose is beneficial for transport across the PN junction thus enhancing the thermoelectric properties. A fundamental working principle of the proposed concept is suggested, along with characterization of power output and output voltages per temperature difference that are close to those one would expect from a conventional thermoelectric generator.

2019 ◽  
Vol 55 (31) ◽  
pp. 4586-4588 ◽  
Author(s):  
Keisuke Awaya ◽  
Akihide Takashiba ◽  
Takaaki Taniguchi ◽  
Michio Koinuma ◽  
Tatsumi Ishihara ◽  
...  

A 1.3 nm-thick nickel hydroxide (p-type, 0.5 nm)/titania (n-type, 0.8 nm) pn junction prepared by lamination of nanosheets improved the onset potential for photoelectrochemical oxidation and increased the photooxidation current, indicating that ultrathin pn junctions suppress the recombination of photo-generated carriers.


2015 ◽  
Vol 1788 ◽  
pp. 13-18
Author(s):  
M. Brast ◽  
S. Axmann ◽  
M. Slawinski ◽  
M. Weingarten ◽  
F. Lindla ◽  
...  

ABSTRACTThe development of efficient large-area organic light emitting diodes (OLED) requires reliable and easily processable charge generation layers (CGL) with low excess voltage drop and high optical transparency. OVPD offers the advantage of a precise control of layer morphology, composition and thickness and is a powerful method for the deposition of advanced OLED designs. In this work, electrical doping of organic semiconductors using OVPD is investigated and applied to stacked OLED utilizing inorganic/organic CGL. The organic p-type dopant NDP-9 of Novaled GmbH is used for doping the hole transport material N,N‘-diphenyl-N,N‘-bis(1-naphthylphenyl)-1,1‘-biphenyl-4,4‘-diamine (α-NPD) in an AIXTRON OVPD tool. A doping concentration of 8 vol.% of NDP-9 in α-NPD is found optimal for hole injection as well as conductivity. This dopant concentration was employed in CGL with the structure: electron transport material/LiF/Al/α-NPD:8 vol.% NDP-9. External quantum efficiencies (EQE) of 15%, 35% and 50% and luminous efficiencies of 37 lm/W, 45 lm/W and 45 lm/W at 1000 cd/m2 are demonstrated for single, double- and triple-unit green phosphorescent OLED, respectively.


2020 ◽  
Vol 6 (8(77)) ◽  
pp. 21-23
Author(s):  
S.N. Sarmasov ◽  
R.Sh. Rahimov ◽  
T.Sh. Abdullayev

The effect of oxygen adsorption on the conductivity of PbTe films is studied. Pn junctions based on PbTe films are photosensitive in the IR spectral region with a maximum photosensitivity of 𝜆𝑚𝑎𝑥 microns. The tunneling mechanism of current flow through the pn junction is shown.


2021 ◽  
Vol 13 (1) ◽  
Author(s):  
Muhammad Naqi ◽  
Kyung Hwan Choi ◽  
Hocheon Yoo ◽  
Sudong Chae ◽  
Bum Jun Kim ◽  
...  

AbstractLow-temperature-processed semiconductors are an emerging need for next-generation scalable electronics, and these semiconductors need to feature large-area fabrication, solution processability, high electrical performance, and wide spectral optical absorption properties. Although various strategies of low-temperature-processed n-type semiconductors have been achieved, the development of high-performance p-type semiconductors at low temperature is still limited. Here, we report a unique low-temperature-processed method to synthesize tellurium nanowire networks (Te-nanonets) over a scalable area for the fabrication of high-performance large-area p-type field-effect transistors (FETs) with uniform and stable electrical and optical properties. Maximum mobility of 4.7 cm2/Vs, an on/off current ratio of 1 × 104, and a maximum transconductance of 2.18 µS are achieved. To further demonstrate the applicability of the proposed semiconductor, the electrical performance of a Te-nanonet-based transistor array of 42 devices is also measured, revealing stable and uniform results. Finally, to broaden the applicability of p-type Te-nanonet-based FETs, optical measurements are demonstrated over a wide spectral range, revealing an exceptionally uniform optical performance.


Materials ◽  
2021 ◽  
Vol 14 (4) ◽  
pp. 901
Author(s):  
Gizem Acar ◽  
Muhammad Javaid Iqbal ◽  
Mujeeb Ullah Chaudhry

Organic light-emitting field-effect transistors (LEFETs) provide the possibility of simplifying the display pixilation design as they integrate the drive-transistor and the light emission in a single architecture. However, in p-type LEFETs, simultaneously achieving higher external quantum efficiency (EQE) at higher brightness, larger and stable emission area, and high switching speed are the limiting factors for to realise their applications. Herein, we present a p-type polymer heterostructure-based LEFET architecture with electron and hole injection interlayers to improve the charge injection into the light-emitting layer, which leads to better recombination. This device structure provides access to hole mobility of ~2.1 cm2 V−1 s−1 and EQE of 1.6% at a luminance of 2600 cd m−2. Most importantly, we observed a large area emission under the entire drain electrode, which was spatially stable (emission area is not dependent on the gate voltage and current density). These results show an important advancement in polymer-based LEFET technology toward realizing new digital display applications.


2014 ◽  
Vol 43 (6) ◽  
pp. 2376-2383 ◽  
Author(s):  
R. Chavez ◽  
S. Angst ◽  
J. Hall ◽  
J. Stoetzel ◽  
V. Kessler ◽  
...  

2001 ◽  
Vol 80-81 ◽  
pp. 47-52 ◽  
Author(s):  
Isabel Ferreira ◽  
Rodrigo Martins ◽  
A. Cabrita ◽  
Francisco Manuel Braz Fernandes ◽  
Elvira Fortunato

2008 ◽  
Vol 1069 ◽  
Author(s):  
Ryoji Kosugi ◽  
Toyokazu Sakata ◽  
Yuuki Sakuma ◽  
Tsutomu Yatsuo ◽  
Hirofumi Matsuhata ◽  
...  

ABSTRACTIn practical use of the SiC power MOSFETs, further reduction of the channel resistance, high stability under harsh environments, and also, high product yield of large area devices are indispensable. Pn diodes with large chip area have been already reported with high fabrication yield, however, there is few reports in terms of the power MOSFETs. To clarify the difference between the simple pn diodes and power MOSFETs, we have fabricated four pn-type junction TEGs having the different structural features. Those pn junctions are close to the similar structure of DIMOS (Double-implanted MOS) step-by-step from the simple pn diodes. We have surveyed the V-I characteristics dependence on each structural features over the 2inch wafer. Before their fabrication, we formed grid patterns with numbering over the 2inch wafer, then performed the synchrotron x-ray topography observation. This enables the direct comparison the electrical and spectrographic characteristics of each pn junctions with the fingerprints of defects.Four structural features from TypeA to TypeD are as follows. TypeA is the most simple structure as same as the standard pn diodes formed by Al+ ion implantation (I/I), except that the Al+ I/I condition conforms to that of the p-well I/I in the DIMOS. The JTE structure was used for the edge termination on all junctions. While the TypeA consists of one p-type region, TypeB and TypeC consists of a lot of p-wells. The difference of Type B and C is a difference of the oxide between the adjacent p-wells. The oxide of TypeB consists of the thick field oxide, while that of TypeC consists of the thermal oxide corresponding to the gate oxide in the DIMOS. In the TypeD structure, n+ region corresponding to the source in the DIMOS was added by the P+ I/I. The TypeD is the same structure of the DIMOS, except that the gate and source contacts are shorted. The V-I measurements of the pn junctions are performed using the KEITHLEY 237 voltage source meters with semi-auto probe machine. An active area of the fabricated pn junctions TEGs are 150um2 and 1mm2. Concentration and thickness of the drift layer are 1e16cm−3 and 10um, respectively.In order to compare the V-I characteristics of fabricated pn junctions with their defects information that obtained from x-ray topography measurements directly, the grid patterns are formed before the fabrication. The grid patterns were formed over the 2inch wafer by the SiC etching. The synchrotron x-ray topography measurements are carried out at the Beam-Line 15C in Photon-Factory in High-Energy-Accelerator-Research-Organization. Three diffraction conditions, g=11-28, -1-128, and 1-108, are chosen in grazing-incidence geometry (improved Berg-Barrett method).In the presentation, the V-I characteristics mapping on the 2inch wafer for each pn junctions, and the comparison of V-I characteristics with x-ray topography will be reported.


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