High-Density Feedthrough Technology for Hermetic Biomedical Micropackaging

2013 ◽  
Vol 1572 ◽  
Author(s):  
Emma C. Gill ◽  
John Antalek ◽  
Fred M. Kimock ◽  
Patrick J. Nasiatka ◽  
Ben P. McIntosh ◽  
...  

ABSTRACTImplantable electronic biomedical devices are used clinically to diagnose and treat an increasing number of medical conditions. Such devices typically employ hermetic packages that often incorporate electrical feedthroughs made with conventional ceramic-to-metal bonding technologies. This sealing technology is well established and provides robust hermetic seals, but is limited in both the number and spacing of electrical leads. Emerging devices for interfacing with the human nervous system, however, will require a large number of external electrical leads implemented in a miniaturized packaging configuration. Commercially available feedthrough technologies are currently incapable of providing external electrical contacts with spacings as small as 200 to 400 microns, and thus are neither compatible with integrated circuit I/O (input/output) pad spacings nor with miniature implantable packages. We report the development of a hermetic high-density feedthrough (HDF) technology that allows for conductive path densities as high as 1,000 per cm2, and that is capable of supporting neural interface devices. The fabrication process utilizes multilayer high temperature co-fired ceramic (HTCC) technology in conjunction with platinum leads. Before co-firing, green alumina substrates are interleaved with linear, parallel Pt trace arrays in either wire or thin foils to form the electrical feedthroughs. Layered stacks of spatially isolated traces are first compacted into a composite, and then fired to achieve densification. After firing, the densified multilayered composite compacts are sliced perpendicular to the Pt traces and lapped to produce multiple feedthrough arrays with a high density of leads (conductors). Both hermeticity and biocompatibility of such implantable feedthroughs are important, as both moisture and positive mobile ion contamination from the saline environment of the human body can lead to compromised performance or catastrophic failure. HDFs fabricated using this process with 100 conductors and lead-to-lead spacings as low as 400 microns have been helium leak tested repeatedly and found to exceed industry-accepted standards with helium leak rates in the range of 10–11 mbar-l/s. The spacing of the current prototype matches industry standard neural interface technology, and can be scaled to higher densities with lead-to-lead spacings as small as 200 microns. The reported HDF process has several distinct advantages over prior approaches, including the provision of a large number of conductive feedthrough leads suitable for flip-chip bonding with sub-mm lead-to-lead spacings (pitch), and the incorporation of materials (alumina and platinum) that are already used in medical implants. The implementation of such an HDF technology allows for significant package miniaturization, allowing greater flexibility in surgical placement as well as less invasive procedures for implantable electronic biomedical devices.

2015 ◽  
Vol 12 (4) ◽  
pp. 219-225
Author(s):  
Charles G. Woychik ◽  
Sangil Lee ◽  
Scott McGrath ◽  
Sitaram Arkalgud

The challenge for three-dimensional integrated circuit assembly is how to manage warpage and thin wafer handling to achieve a high assembly yield and to ensure that the final structure can pass the specified reliability requirements. Our test vehicles have microbumped die with pitches ranging from 120 μm down to 60 μm. The high density of pads and the large die size make it extremely challenging to ensure that all of the microbump interconnects are attached to a thin Si interposer (ITP). In addition, the low standoff between the die and ITP makes it difficult to underfill. A likely approach is to first attach the die to the ITP and then the die/ITP subassembly to the substrate. In this scenario, the die/ITP subassembly is comparable to a monolithic Si die that can be flip chip attached to the substrate. In this article, we discuss various assembly options and the challenges posed by each. In this investigation, we will propose the best method to do two-and-half-dimensional assembly in an outsourced assembly and test facility.


Alloy Digest ◽  
1969 ◽  
Vol 18 (7) ◽  

Abstract Sylvania WN-103 is a machinable tungsten-base alloy combining high density with high strength in both compression and tension. It is recommended for counterweights, gyroscope components and high current electrical contacts. This datasheet provides information on composition, physical properties, hardness, elasticity, tensile properties, and shear strength as well as creep. It also includes information on forming, heat treating, machining, and joining. Filing Code: W-13. Producer or source: Sylvania Electric Products Inc..


Alloy Digest ◽  
1969 ◽  
Vol 18 (1) ◽  

Abstract Sylvania WN-102 is a tungsten-base alloy combining high density with high strength in both compression and tension. It is recommended for radioactive shielding, counterweights, electrical contacts for high currents, gyroscopes, flywheels and governors. This datasheet provides information on composition, physical properties, hardness, elasticity, and tensile properties as well as creep. It also includes information on forming, machining, and joining. Filing Code: W-12. Producer or source: Sylvania Electric Products Inc..


VLSI Design ◽  
2015 ◽  
Vol 2015 ◽  
pp. 1-7 ◽  
Author(s):  
Xiao Wang ◽  
Zelin Shi

Being an essential part of infrared readout integrated circuit, correlated double sampling (CDS) circuits play important roles in both depressing reset noise and conditioning integration signals. To adapt applications for focal planes of large format and high density, a new structure of CDS circuit occupying small layout area is proposed, whose power dissipation has been optimized by using MOSFETs in operation of subthreshold region, which leads to 720 nW. Then the noise calculation model is established, based on which the noise analysis has been carried out by the approaches of transfer function and numerical simulations using SIMULINK and Verilog-A. The results are in good agreement, demonstrating the validity of the present noise calculation model. Thermal noise plays a dominant role in the long wave situation while 1/f noise is the majority in the medium wave situation. The total noise of long wave is smaller than medium wave, both of which increase with the integration capacitor and integration time increasing.


Micromachines ◽  
2018 ◽  
Vol 9 (11) ◽  
pp. 553 ◽  
Author(s):  
Fikret Yildiz ◽  
Tadao Matsunaga ◽  
Yoichi Haga

This paper presents fabrication and packaging of a capacitive micromachined ultrasonic transducer (CMUT) using anodically bondable low temperature co-fired ceramic (LTCC). Anodic bonding of LTCC with Au vias-silicon on insulator (SOI) has been used to fabricate CMUTs with different membrane radii, 24 µm, 25 µm, 36 µm, 40 µm and 60 µm. Bottom electrodes were directly patterned on remained vias after wet etching of LTCC vias. CMUT cavities and Au bumps were micromachined on the Si part of the SOI wafer. This high conductive Si was also used as top electrode. Electrical connections between the top and bottom of the CMUT were achieved by Au-Au bonding of wet etched LTCC vias and bumps during anodic bonding. Three key parameters, infrared images, complex admittance plots, and static membrane displacement, were used to evaluate bonding success. CMUTs with a membrane thickness of 2.6 µm were fabricated for experimental analyses. A novel CMUT-IC packaging process has been described following the fabrication process. This process enables indirect packaging of the CMUT and integrated circuit (IC) using a lateral side via of LTCC. Lateral side vias were obtained by micromachining of fabricated CMUTs and used to drive CMUTs elements. Connection electrodes are patterned on LTCC side via and a catheter was assembled at the backside of the CMUT. The IC was mounted on the bonding pad on the catheter by a flip-chip bonding process. Bonding performance was evaluated by measurement of bond resistance between pads on the IC and catheter. This study demonstrates that the LTCC and LTCC side vias scheme can be a potential approach for high density CMUT array fabrication and indirect integration of CMUT-IC for miniature size packaging, which eliminates problems related with direct integration.


Author(s):  
C. C. Wang ◽  
T. D. Kudrle ◽  
M. Bancu ◽  
J. Hsiao ◽  
C. H. Mastrangelo

A method for the construction of high density (2.4 mm−2) vertical leads through a pyrex substrate is presented. The pyrex substrate behaves as a TCE (Thermal Coefficient of Expansion) matched interposer that permits anodic bonding of silicon micromirrors on one side and flip-chip bumping of multiplexing electronic chips on its opposite side. Electrical leads consist of 250±25 μm-diameter holes formed by AJM machining and coated with evaporated Au yielding via resistances of 0.5–0.7 Ω. The via holes are sealed with a new spin-cast polyimide tenting process that enables the subsequent patterning of multiple levels of metal using conventional lithographic techniques.


2009 ◽  
Vol 6 (1) ◽  
pp. 6-12 ◽  
Author(s):  
Arne Albertsen ◽  
Koji Koiwai ◽  
Kyoji Kobayashi ◽  
Tomonori Oguchi ◽  
Katsumi Aruga

This paper highlights the possible combination of technologies such as thick film screen printing, ink jet, and post-firing thin film processes in conjunction with laser-drilled fine vias to produce high-density, miniaturized LTCC substrates. To obtain the silver pattern on the inner layers, both conventional thick film printing and ink jet printing (using nano silver particle dispersed ink) were applied on the ceramic green sheets. The ink jet process made it possible to metallize fine lines with line/space = 30/30 μm. For interlayer connections, fine vias of 30 μm in diameter formed by UV laser were used. Then these sheets were stacked on top of each other and fired to obtain a base substrate. On this base substrate, fine copper patterns for flip chip mounting were formed by a thin film process. The surface finish consisted of a nickel passivation and a gold layer deposited by electroless plating. The combination of the three patterning processes for conducting traces and UV laser drilling of fine vias make it appear possible to realize fine pitch LTCC, for example, for flip chip device mounting.


Sign in / Sign up

Export Citation Format

Share Document