Nonvolatile memory MOS capacitors made of CdSe embedded ZrHfO high-k gate dielectric

2013 ◽  
Vol 1562 ◽  
Author(s):  
Chi-Chou Lin ◽  
Yue Kuo
Keyword(s):  
Gate Voltage ◽  
Coulomb Blockade ◽  
Nonvolatile Memory ◽  
Gate Dielectric ◽  
Stress Test ◽  
Charge Trapping ◽  
Differential Resistance ◽  
Mos Capacitors ◽  
Mos Capacitor ◽  
High K

ABSTRACTMOS capacitor composed of nc-CdSe embedded ZrHfO high-k gate dielectric stack was fabricated and characterized for nonvolatile memory functions. Detailed material and electrical properties have been investigated. With a large charge trapping capability, this kind of device can trap electrons or holes depending on the polarity and magnitude of the applied gate voltage. For the same stress time, the device trapped more holes than electrons under the same magnitude of gate voltage but different polarity. The negative differential resistance peak was observed at the room temperature due to the Coulomb blockade effect. The charge trapping mechanism was delineated with the constant voltage stress test. After 10 years of storage, about 56% of trapped charges still remain in the device.

Characterization of LaxHfyO Gate Dielectrics in 4H-SiC MOS Capacitor

2014 ◽  
Vol 778-780 ◽  
pp. 549-552 ◽  
Author(s):  
Jing Hua Xia ◽  
David M. Martin ◽  
Sethu Saveda Suvanam ◽  
Carl Mikael Zetterling ◽  
Mikael Östling
Keyword(s):  
Gate Dielectric ◽  
Gate Dielectrics ◽  
Atomic Layer ◽  
Deposition Process ◽  
Mos Capacitors ◽  
Mos Capacitor ◽  
Layer Deposition ◽  
High K ◽  
Film Characteristics

LaxHfyO nanolaminated thin film deposited using atomic layer deposition process has been studied as a high-K gate dielectric in 4H-SiC MOS capacitors. The electrical and nano-laminated film characteristics were studied with increasing post deposition annealing (PDA) in N2O ambient. The result shows that high quality LaxHfyO nano-laminated thin films with good interface and bulk qualities are fabricated using high PDA temperature.

Temperature Effects on Charge Transfer Mechanisms of nc-ITO Embedded ZrHfO High-k Nonvolatile Memory Devices

2011 ◽  
Vol 1337 ◽  
Author(s):  
Chia-Han Yang ◽  
Yue Kuo ◽  
Chen-Han Lin ◽  
Way Kuo
Keyword(s):  
Gate Voltage ◽  
Nonvolatile Memory ◽  
Charge Retention ◽  
Mos Capacitors ◽  
Dielectric Thin Film ◽  
High K ◽  
Nonvolatile Memory Devices ◽  
High K Dielectric ◽  
Voltage Region ◽  
Large Charge

ABSTRACTThe nanocrystalline ITO embedded Zr-doped HfO2 high-k dielectric thin film has been made into MOS capacitors for nonvolatile memory studies. The devices showed large charge storage densities, large memory windows, and long charge retention times. In this paper, authors investigated the temperature effect on the charge transport and reliability of this kind of device in the range of 25°C to 125°C. The memory window increased with the increase of the temperature. The temperature influenced the trap and detrap of not only the deeply-trapped but also the loosely-trapped charges. The device lost its charge retention capability with the increase of the temperature. The Schottky emission relationship fitted the device in the positive gate voltage region. However, the Frenkel-Poole mechanism was suitable in the negative gate voltage region.

Analysis of 3-Dimensional 4H-SiC MOS Capacitors Grown by Atomic Layer Deposition of Al2O3

2018 ◽  
Vol 924 ◽  
pp. 490-493 ◽  
Author(s):  
Muhammad I. Idris ◽  
Nick G. Wright ◽  
Alton B. Horsfall
Keyword(s):  
Atomic Layer Deposition ◽  
Gate Dielectric ◽  
Atomic Layer ◽  
Oxide Semiconductor ◽  
Mos Capacitors ◽  
Mos Capacitor ◽  
3 Dimensional ◽  
Layer Deposition ◽  
Show Evidence ◽  
Flatband Voltage

3-Dimensional 4H-SiC metal-oxide-semiconductor capacitors have been fabricated to determine the effect of the sidewall on the characteristics of 3-Dimentional gate structures. Al2O3 deposited by Atomic Layer Deposition (ALD) was used as the gate dielectric layer on the trench structure. The 3-D MOS capacitors exhibit increasing accumulation capacitance with excellent linearity as the sidewall area increases, indicating that ALD results in a highly conformal dielectric film. The capacitance – voltage characteristics also show evidence of a second flatband voltage, located at a higher bias than that seen for purely planar devices on the same sample. We also observe that the oxide capacitance of planar and 3-D MOS capacitors increases with temperature. Finally, we have found that the 3-D MOS capacitor has a weaker temperature dependence of flatband voltage in comparison to the conventional planar MOS capacitor due to the incorporation of the (1120) plane in the sidewall.

Charge Trapping Sites in nc-RuO Embedded ZrHfO High-k Nonvolatile Memories

2010 ◽  
Vol 1250 ◽  
Author(s):  
Chen-Han Lin ◽  
Yue Kuo
Keyword(s):  
Dielectric Film ◽  
Electrical Characterization ◽  
Charge Trapping ◽  
Mos Capacitor ◽  
Hole Trapping ◽  
Nonvolatile Memories ◽  
High K ◽  
Voltage Stress ◽  
Retention Characteristics ◽  
Trapping Sites

AbstractMaterials and electrical properties of the MOS capacitor containing nc-RuO embedded in the high-k ZrHfO dielectric film have been studied. The electron- and hole-trapping capacities and trapping sites in this kind of device were investigated using the constant voltage stress method, the frequency-dependent C-V measurement, and the retention characteristics. The negligible charge trapping phenomenon in the non-embedded device rules out the possibility of any trapping site in the bulk ZrHfO film or at the Si/ZrHfO interface. The electrical characterization result suggests that electrons are trapped in the bulk nc-RuO. However, holes have two possible trapping sites, i.e., in the bulk nc-RuO or at the nc-RuO/ZrHfO interface.

scholarly journals Electrical and Optical Characteristics of SSI-LED Made from Capacitor Containing Tri-Layer WOx Embedded Zr-Doped HfOx Gate Dielectric

2021 ◽  
Author(s):  
Wen-Shan Lin ◽  
Yue Kuo
Keyword(s):  
Dielectric Layer ◽  
Gate Dielectric ◽  
Gate Dielectrics ◽  
Optical Characteristics ◽  
Mos Capacitors ◽  
Mos Capacitor ◽  
Light Emitting ◽  
Light Emitting Devices ◽  
Warm White Light ◽  
The Difference

Abstract Solid-state incandescent light emitting devices made from MOS capacitors with the WOx embedded Zr-doped HfOx gate dielectric were characterized for electrical and optical characteristics. Devices made from capacitors containing Zr-doped HfOx and WOx, gate dielectrics were also fabricated for comparison. The device with the WOx embedded gate dielectric layer had electrical and light emitting characteristics between that with WOx gate dielectric layer and that with the Zr-doped HfOx but no WOx embedded gate dielectric layer. The difference can be explained by the nano-resistor formation process and the content of the high emissivity W in the nano-resistor. The device made from the WOx embedded Zr-doped HfOx gate dielectric MOS capacitor is applicable to areas where uniform emission of warm white light is required.

Electrical Characteristics of TaOxNy/ZrSixOy Stack Gate Dielectric for MOS Device Applications

2001 ◽  
Vol 670 ◽  
Author(s):  
Hyungsuk Jung ◽  
Hyundoek Yang ◽  
Kiju Im ◽  
Hyunsang Hwang
Keyword(s):  
Interfacial Layer ◽  
Silicon Oxide ◽  
Gate Dielectric ◽  
Oxide Thickness ◽  
Tem Analysis ◽  
Mos Capacitors ◽  
Zirconium Silicate ◽  
Transmission Electron ◽  
High K ◽  
Device Applications

ABSTRACTThis letter describes a unique process for the preparation of high quality tantalum oxynitride (TaOxNy) with zirconium silicate (ZrSixOy) as an interfacial layer for use in gate dielectric applications. Compared with conventional native silicon oxide and oxynitride as an interfacial layer, tantalum oxynitride (TaOxNy) MOS capacitors using zirconium silicate (ZrSixOy) as an interfacial layer exhibit lower leakage current levels at the same equivalent oxide thickness. We were able to confirm TaOxNy/ZrSixOy stack structure by auger electron spectroscopy (AES) and transmission electron microscope (TEM) analysis. The estimated dielectric constant of TaOxNy and ZrSixOywere approximately 67 and 7, respectively. The zirconium silicate is a promising interfacial layer for future high-k gate dielectric applications.

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