Heterogeneous Integration of LSI Amplifier and the Tactile Sensor Using Stacking and Through-Si-Via Techniques

2012 ◽  
Vol 1427 ◽  
Author(s):  
Masayuki Sohgawa ◽  
Hokuto Yokoyama ◽  
Takeshi Kanashima ◽  
Masanori Okuyama ◽  
Haruo Noma
Keyword(s):  
Standard Deviation ◽  
Output Voltage ◽  
Tactile Sensor ◽  
Heterogeneous Integration ◽  
Wire Length ◽  
Shear Forces ◽  
Voltage Standard ◽  
Sacrificial Etching ◽  
On Chip ◽  
Device Size

ABSTRACTWe have developed the tactile sensor using the microcantilevers with strain gauge film which can detect normal and shear forces simultaneously. In this work, the tactile sensor and the IC amplifier have been integrated heterogeneously to shorten the wire length by chip-on-chip stacking and reduce the noise in the output voltage. Standard deviation of the noise can be reduced from 27.6 mV to 3.3 mV by heterogeneous integration of the tactile sensor and the IC amplifier using Au wire bonding. By this heterogeneous integration, the device size and wiring numbers can be reduced, and installation of more sensors is allowed on fingertips of the robot. Moreover, through-silicon-via (TSV) holes were fabricated to mount an IC amplifier on the backside of the sensor chip, instead of using Au wires. Although TSV can be fabricated successfully, resistance to sacrificial etching process is problem. As a result, Si3N4 used instead of SiO2 has improved insulation between TSVs.

scholarly journals An Automatic Offset Calibration Method for Differential Charge-Based Capacitance Measurement

2021 ◽  
Vol 11 (2) ◽  
pp. 22
Author(s):  
Umberto Ferlito ◽  
Alfio Dario Grasso ◽  
Michele Vaiana ◽  
Giuseppe Bruno
Keyword(s):  
Standard Deviation ◽  
Output Voltage ◽  
Process Variations ◽  
Calibration Method ◽  
Capacitance Measurement ◽  
Effective Technique ◽  
Fully Integrated ◽  
Front End ◽  
Novel Method ◽  
On Chip

Charge-Based Capacitance Measurement (CBCM) technique is a simple but effective technique for measuring capacitance values down to the attofarad level. However, when adopted for fully on-chip implementation, this technique suffers output offset caused by mismatches and process variations. This paper introduces a novel method that compensates the offset of a fully integrated differential CBCM electronic front-end. After a detailed theoretical analysis of the differential CBCM topology, we present and discuss a modified architecture that compensates mismatches and increases robustness against mismatches and process variations. The proposed circuit has been simulated using a standard 130-nm technology and shows a sensitivity of 1.3 mV/aF and a 20× reduction of the standard deviation of the differential output voltage as compared to the traditional solution.

Packaging without the Package - A More Holistic Moore's Law

2017 ◽  
Vol 2017 (S1) ◽  
pp. 1-40
Author(s):  
Subramanian S. Iyer (Subu)
Keyword(s):  
System Integration ◽  
System Level ◽  
Heterogeneous Integration ◽  
Power Performance ◽  
Wafer Level ◽  
Innovative Materials ◽  
Barrier To Entry ◽  
On Chip ◽  
Market Consolidation ◽  
Conventional Systems

Silicon features have scaled by over 1500X for over six decades, and with the adoption of innovative materials delivered better power-performance, density and till recently, cost per function, almost every generation. This has spawned a vibrant system-on-chip (SoC) approach, where progressively more function has been integrated on a single die. The integration of multiple dies on packages and boards has, however, scaled only modestly by a factor of three to five times. However, as SoCs have become bigger and more complex, the Non-Recurring Engineering (NRE) Charge and time to market have both ballooned out of control leading to ever increasing market consolidation. We need to address this problem through novel methods of system Integration. With the well-documented slowing down of scaling and the advent of the Internet of Things, there is a focus on heterogeneous integration and system-level scaling. Packaging itself is undergoing a transformation that focuses on overall system performance through integration rather than on packaging individual components. We propose ways in which this transformation can evolve to provide a significant value at the system level while providing a significantly lower barrier to entry compared with a chip-based SoC approach that is currently used. More importantly it will allow us to re-architect systems in a very significant way. This transformation is already under way with 3-D stacking of dies, Wafer level fan-out processing, and will evolve to make heterogeneous integration the backbone of a new SoC methodology, extending to integrate entire Systems on Wafers (SoWs). We will describe the technology we use and the results to-date. This has implications in redefining the memory hierarchy in conventional systems and in neuromorphic systems. We extend these concepts to flexible and biocompatible electronics.

scholarly journals On-chip Mach-Zehnder interferometer for OCT systems

2018 ◽  
Vol 7 (1-2) ◽  
pp. 103-106 ◽  
Author(s):  
Ton G. van Leeuwen ◽  
Imran B. Akca ◽  
Nikolaos Angelou ◽  
Nicolas Weiss ◽  
Marcel Hoekman ◽  
...  
Keyword(s):  
Zehnder Interferometer ◽  
Depth Range ◽  
Axial Resolution ◽  
Swept Source ◽  
System A ◽  
Swept Source Oct ◽  
On Chip ◽  
Device Size ◽  
Mach Zehnder Interferometer

AbstractBy using integrated optics, it is possible to reduce the size and cost of a bulky optical coherence tomography (OCT) system. One of the OCT components that can be implemented on-chip is the interferometer. In this work, we present the design and characterization of a Mach-Zehnder interferometer consisting of the wavelength-independent splitters and an on-chip reference arm. The Si3N4was chosen as the material platform as it can provide low losses while keeping the device size small. The device was characterized by using a home-built swept source OCT system. A sensitivity value of 83 dB, an axial resolution of 15.2 μm (in air) and a depth range of 2.5 mm (in air) were all obtained.

scholarly journals Tactile Slippage Analysis in Optical Three-Axis Tactile Sensor for Robotic Hand

2013 ◽  
Vol 465-466 ◽  
pp. 1375-1379
Author(s):  
Hanafiah Yussof ◽  
Zahari Nur Ismarrubie ◽  
Ahmad Khushairy Makhtar ◽  
Masahiro Ohka ◽  
Siti Nora Basir
Keyword(s):  
Control Algorithm ◽  
Tactile Sensor ◽  
Robotic Hand ◽  
Robot Hand ◽  
Robot Arm ◽  
Tactile Sensors ◽  
Shear Forces ◽  
Improve Performance ◽  
Robot Arm Control ◽  
Two Phases

This paper presents experimental results of object handling motions to evaluate tactile slippage sensation in a multi fingered robot arm with optical three-axis tactile sensors installed on its two hands. The optical three-axis tactile sensor is a type of tactile sensor capable of defining normal and shear forces simultaneously. Shear force distribution is used to define slippage sensation in the robot hand system. Based on tactile slippage analysis, a new control algorithm was proposed. To improve performance during object handling motions, analysis of slippage direction is conducted. The control algorithm is classified into two phases: grasp-move-release and grasp-twist motions. Detailed explanations of the control algorithm based on the existing robot arm control system are presented. The experiment is conducted using a bottle cap, and the results reveal good performance of the proposed control algorithm to accomplish the proposed object handling motions.

Support Force Measures of Midsized Men in Seated Positions

2006 ◽  
Vol 129 (1) ◽  
pp. 58-65 ◽  
Author(s):  
Tamara Reid Bush ◽  
Robert P. Hubbard
Keyword(s):  
Standard Deviation ◽  
Repeated Measures ◽  
Average Weight ◽  
Average Height ◽  
Shear Forces ◽  
Normal Forces ◽  
Repeated Measures Analysis ◽  
Support Force ◽  
Inclination Angles ◽  
Four Levels

Two areas not well researched in the field of seating mechanics are the distribution of normal and shear forces, and how those forces change with seat position. The availability of these data would be beneficial for the design and development of office, automotive and medical seats. To increase our knowledge in the area of seating mechanics, this study sought to measure the normal and shear loads applied to segmental supports in 12 seated positions, utilizing three inclination angles and four levels of seat back articulation that were associated with automotive driving positions. Force data from six regions, including the thorax, sacral region, buttocks, thighs, feet, and hand support were gathered using multi-axis load cells. The sample contained 23 midsized subjects with an average weight of 76.7kg and a standard deviation of 4.2kg, and an average height of 1745mm with a standard deviation of 19mm. Results were examined in terms of seat back inclination and in terms of torso articulation for relationships between seat positions and support forces. Using a repeated measures analysis, significant differences (p<0.05) were identified for normal forces relative to all inclination angles except for forces occurring at the hand support. Other significant differences were observed between normal forces behind the buttocks, pelvis, and feet for torso articulations. Significant differences in the shear forces occurred under the buttocks and posterior pelvis during changes in seat back inclination. Significant differences in shear forces were also identified for torso articulations. These data suggest that as seat back inclination or torso articulation change, significant shifts in force distribution occur.

Structure Optimization of Piezoelectric Micromachined Modal Gyroscope

2011 ◽  
Vol 130-134 ◽  
pp. 3377-3380
Author(s):  
Xiao Jun Hu ◽  
Xiao Sheng Wu ◽  
Zheng Wang ◽  
Wen Yuan Chen ◽  
Wei Ping Zhang
Keyword(s):  
Angular Velocity ◽  
Harmonic Analysis ◽  
Coriolis Force ◽  
Output Voltage ◽  
Working Condition ◽  
Operation Mode ◽  
Structure Optimization ◽  
Mass Spring ◽  
Quantitative Indicators ◽  
Device Size

This paper reports a novel kind of solid micro-gyroscope, which is called piezoelectric micromachined modal gyroscope (PMMG). PMMG has large stiffness and robust resistance to shake and strike because there is no evident mass-spring component in its structure. This work focused on quantitative optimization of the gyroscope, which is still blank for such gyroscope. A set of quantitative indicators were developed to optimize the operation mode and corresponding device size was obtained. By FEM, the harmonic analysis was conducted to find the way to efficiently actuate the operation mode needed. At last, the Coriolis analysis was conducted to show the relation between angular velocity and differential output voltage by the Coriolis force under working condition.

scholarly journals CAPACITOR-LESS LOW-DROPOUT VOLTAGE REGULATOR

2014 ◽  
pp. 50-55
Author(s):  
SRIRANGANATHA SAGAR.K.N ◽  
POORNIMA N. ◽  
VIJAYA KUMAR. V
Keyword(s):  
Output Voltage ◽  
Total Error ◽  
Cmos Technology ◽  
Damping Factor ◽  
Frequency Compensation ◽  
Load Variations ◽  
Power Supply Rejection Ratio ◽  
Control Frequency ◽  
Low Dropout Regulator ◽  
On Chip

A 1.2-V 40-mA capacitor-free CMOS low-dropout regulator (LDO) for system-on-chip applications to reduce board space and external pins is presented. By utilizing damping-factor control frequency compensation on the advanced LDO structure, the proposed LDO provides high stability, as well as fast line and load transient responses, even in capacitorfree operation. The proposed LDO has been implemented in a tsmc65nm CMOS technology, and the total error of the output voltage due to line and load variations is less. Moreover, the output voltage can recover with ≈2.3μs for full load current changes. The power-supply rejection ratio at 1 MHz is 26 dB.

IMPROVEMENT OF POWER EFFICIENCY AND OUTPUT VOLTAGE RIPPLE OF EMBEDDED DC–DC CONVERTERS WITH THREE STEP DOWN RATIOS

2012 ◽  
Vol 21 (01) ◽  
pp. 1250007 ◽  
Author(s):  
KAUSHIK BHATTACHARYYA ◽  
P. V. RATNA KUMAR ◽  
PRADIP MANDAL
Keyword(s):  
Power Efficiency ◽  
Output Voltage ◽  
Cmos Process ◽  
Switched Capacitor ◽  
Switching Scheme ◽  
Time Interleaving ◽  
Regulation Scheme ◽  
Voltage Ripple ◽  
Switched Capacitor Converter ◽  
On Chip

In this paper three embedded switched capacitor based DC–DC converters targeting Vdd/2, 2Vdd/3, and Vdd/3 output voltages have been designed with improved power efficiency and output voltage ripple. The performance of each of the converter is improved by nonoverlapped rotational time interleaving (NRTI) switching scheme. Current regulation scheme is included with each of the above NRTI switched capacitor converter to achieve better load and line regulation. The proposed converters are designed and simulated in a 0.18 μm n-well CMOS process with the total flying capacitance of 330 pF and load capacitor of 50 pF. The capacitance values are kept within on-chip implementable range. The maximum power efficiency and the output voltage ripple of the integrated NRTI DC–DC converters targeted for Vdd/2, 2Vdd/3 and Vdd/3 output generation are 71.5% and 5 mV, 69.23% and 13.27 mV and 58.09% and 10.5 mV, respectively.

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