HIGH FREQUENCY TOP-GATED GRAPHENE RF AMBIPOLAR FETs USING LARGE-AREA CVD GRAPHENE AND ADVANCED DIELECTRICS

2011 ◽  
Vol 1283 ◽  
Author(s):  
Osama M. Nayfeh ◽  
Madan Dubey

ABSTRACTAmbipolar top-gated field effect transistors (FETs) based on large area Cu catalyzed CVD-grown monolayer graphene interfaced to advanced dielectrics have been constructed and examined both for their material and electrical qualities. Interfacing of the graphene with novel insulators/substrates could be tailored for the particular application and provide for enhanced device functionality. In contrast to graphene FETs using SiO2-based top-gate dielectric, which show asymmetric electron/hole mobility (with larger hole mobility), and Dirac point shifted to positive levels, FETs constructed using advanced AlN show Dirac point almost near neutral levels and near symmetric electron/hole mobility. The DP is shifted likely due to compensation of the intrinsic p-type doping by n-type doping introduced by the AlN deposition and potentially via a contribution of polarization-induced carrier density. Finally, we demonstrate a top-gated graphene FET with the first observation of RF operation with GHz cut-off frequency based on large area CVD graphene.

2011 ◽  
Vol 20 (03) ◽  
pp. 669-677
Author(s):  
OSAMA M. NAYFEH ◽  
TONY IVANOV ◽  
JAMES WILSON ◽  
ROBERT PROIE ◽  
MADAN DUBEY

Graphene transistors using large area chemical-vapor-deposited (CVD) monolayer graphene and advanced dielectric stacks are constructed and examined. Top-gated devices with a SiO 2/ Al 2 O 3 gate-dielectric have a Dirac Point (DP) located at less than 5 V and asymmetric electron/hole mobility. In contrast, devices based on an advanced AlN interfacial layer have a DP located near 0V and a near symmetric carrier mobility- characteristics that could be more suitable for applications that require ambipolar behavior and low-power operation. For the first time, a measured RF cut-off frequency range of 1GHz is measured for top-gated transistors using CVD graphene. The results are of importance for the realization of graphene based, wafer-scale, high frequency electronics.


2021 ◽  
Vol 13 (1) ◽  
Author(s):  
Muhammad Naqi ◽  
Kyung Hwan Choi ◽  
Hocheon Yoo ◽  
Sudong Chae ◽  
Bum Jun Kim ◽  
...  

AbstractLow-temperature-processed semiconductors are an emerging need for next-generation scalable electronics, and these semiconductors need to feature large-area fabrication, solution processability, high electrical performance, and wide spectral optical absorption properties. Although various strategies of low-temperature-processed n-type semiconductors have been achieved, the development of high-performance p-type semiconductors at low temperature is still limited. Here, we report a unique low-temperature-processed method to synthesize tellurium nanowire networks (Te-nanonets) over a scalable area for the fabrication of high-performance large-area p-type field-effect transistors (FETs) with uniform and stable electrical and optical properties. Maximum mobility of 4.7 cm2/Vs, an on/off current ratio of 1 × 104, and a maximum transconductance of 2.18 µS are achieved. To further demonstrate the applicability of the proposed semiconductor, the electrical performance of a Te-nanonet-based transistor array of 42 devices is also measured, revealing stable and uniform results. Finally, to broaden the applicability of p-type Te-nanonet-based FETs, optical measurements are demonstrated over a wide spectral range, revealing an exceptionally uniform optical performance.


Materials ◽  
2021 ◽  
Vol 14 (4) ◽  
pp. 901
Author(s):  
Gizem Acar ◽  
Muhammad Javaid Iqbal ◽  
Mujeeb Ullah Chaudhry

Organic light-emitting field-effect transistors (LEFETs) provide the possibility of simplifying the display pixilation design as they integrate the drive-transistor and the light emission in a single architecture. However, in p-type LEFETs, simultaneously achieving higher external quantum efficiency (EQE) at higher brightness, larger and stable emission area, and high switching speed are the limiting factors for to realise their applications. Herein, we present a p-type polymer heterostructure-based LEFET architecture with electron and hole injection interlayers to improve the charge injection into the light-emitting layer, which leads to better recombination. This device structure provides access to hole mobility of ~2.1 cm2 V−1 s−1 and EQE of 1.6% at a luminance of 2600 cd m−2. Most importantly, we observed a large area emission under the entire drain electrode, which was spatially stable (emission area is not dependent on the gate voltage and current density). These results show an important advancement in polymer-based LEFET technology toward realizing new digital display applications.


2015 ◽  
Vol 2015 ◽  
pp. 1-5 ◽  
Author(s):  
W. Wang ◽  
C. Hu ◽  
S. Y. Li ◽  
F. N. Li ◽  
Z. C. Liu ◽  
...  

Investigation of Zr-gate diamond field-effect transistor withSiNxdielectric layers (SD-FET) has been carried out. SD-FET works in normally on depletion mode with p-type channel, whose sheet carrier density and hole mobility are evaluated to be 2.17 × 1013 cm−2and 24.4 cm2·V−1·s−1, respectively. The output and transfer properties indicate the preservation of conduction channel because of theSiNxdielectric layer, which may be explained by the interface bond of C-N. High voltage up to −200 V is applied to the device, and no breakdown is observed. For comparison, another traditional surface channel FET (SC-FET) is also fabricated.


2001 ◽  
Vol 79 (25) ◽  
pp. 4246-4248 ◽  
Author(s):  
C. W. Leitz ◽  
M. T. Currie ◽  
M. L. Lee ◽  
Z.-Y. Cheng ◽  
D. A. Antoniadis ◽  
...  

2021 ◽  
Vol 8 (8) ◽  
pp. 210554
Author(s):  
Lin Tao ◽  
Lixiang Han ◽  
Qian Yue ◽  
Bin Yao ◽  
Yujue Yang ◽  
...  

Carrier mobility is one of most important figures of merit for materials that can determine to a large extent the corresponding device performances. So far, extensive efforts have been devoted to the mobility improvement of two-dimensional (2D) materials regarded as promising candidates to complement the conventional semiconductors. Graphene has amazing mobility but suffers from zero bandgap. Subsequently, 2D transition-metal dichalcogenides benefit from their sizable bandgap while the mobility is limited. Recently, the 2D elemental materials such as the representative black phosphorus can combine the high mobility with moderate bandgap; however the air-stability is a challenge. Here, we report air-stable tellurium flakes and wires using the facile and scalable physical vapour deposition (PVD) method. The prototype field-effect transistors were fabricated to exhibit high hole mobility up to 1485 cm 2 V −1 s −1 at room temperature and 3500 cm 2 V −1 s −1 at low temperature (2 K). This work can attract numerous attentions on this new emerging 2D tellurium and open up a new way for exploring high-performance optoelectronics based on the PVD-grown p-type tellurium.


2019 ◽  
Vol 9 (6) ◽  
pp. 1110 ◽  
Author(s):  
Xiao-Mei Zhang ◽  
Sian-Hong Tseng ◽  
Ming-Yen Lu

Two-dimensional (2D) MoS2 has recently become of interest for applications in broad range photodetection due to their tunable bandgap. In order to develop 2D MoS2 photodetectors with ultrafast response and high responsivity, up-scalable techniques for realizing controlled p-type doping in MoS2 is necessary. In this paper, we demonstrate a p-type multilayer MoS2 photodetector with selective-area doping using CHF3 plasma treatment. Microscopic and spectroscopic characterization techniques, including atomic force microscopy (AFM) and X-ray photoelectron spectroscopy (XPS), are used to investigate the morphological and electrical modification of the p-type doped MoS2 surface after CHF3 plasma treatment. Back-gated p-type MoS2 field-effect transistors (FETs) are fabricated with an on/off current ratio in the order of 103 and a field-effect mobility of 65.2 cm2V−1s−1. They exhibit gate-modulated ultraviolet photodetection with a rapid response time of 37 ms. This study provides a promising approach for the development of mild plasma-doped MoS2 as a 2D material in post-silicon electronic and optoelectronic device applications.


2016 ◽  
Vol 6 (1) ◽  
Author(s):  
S. Goniszewski ◽  
M. Adabi ◽  
O. Shaforost ◽  
S. M. Hanham ◽  
L. Hao ◽  
...  

Abstract Correlations between the level of p-doping exhibited in large area chemical vapour deposition (CVD) graphene field effect transistor structures (gFETs) and residual charges created by a variety of surface treatments to the silicon dioxide (SiO2) substrates prior to CVD graphene transfer are measured. Beginning with graphene on untreated thermal oxidised silicon, a minimum conductivity (σ min ) occurring at gate voltage V g  = 15 V (Dirac Point) is measured. It was found that more aggressive treatments (O2 plasma and UV Ozone treatments) further increase the gate voltage of the Dirac point up to 65 V, corresponding to a significant increase of the level of p-doping displayed in the graphene. An electrowetting model describing the measured relationship between the contact angle (θ) of a water droplet applied to the treated substrate/graphene surface and an effective gate voltage from a surface charge density is proposed to describe biasing of V g at σ min and was found to fit the measurements with multiplication of a correction factor, allowing effective non-destructive approximation of substrate added charge carrier density using contact angle measurements.


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