Tunneling Currents in Nanoscale high-κ MOS Structures

2011 ◽  
Vol 1292 ◽  
Author(s):  
Andrés Vercik
Keyword(s):  
Integrated Circuits ◽  
Power Dissipation ◽  
Inversion Layer ◽  
Tunneling Current ◽  
Semiconductor Surface ◽  
Leakage Currents ◽  
Additional Layer ◽  
Promising Strategy ◽  
Tunneling Currents ◽  
Mos Structures

ABSTRACTFurther improvements of integrated circuits depend on the continuous downscaling of MOSFET´s, well beyond the limits for which direct tunneling currents are acceptable. These leakage currents affect both the stand-by power dissipation and the formation of the inversion layer ate the semiconductor surface, i.e., the channel formation. The most promising strategy to overcome this problem is the use of high-κ insulator in substitution of or as an additional layer on the traditional silicon dioxide. The aim of this work is using a recently developed theory to describe tunneling from inversion layers for high-κ insulators or stacks and analyze the effects of tunneling current on the thermal equilibrium in these cases.

An Improved CAL Register File with Dual-Threshold Technique for Leakage Reduction

2010 ◽  
Vol 159 ◽  
pp. 186-191 ◽  
Author(s):  
Jian Ping Hu ◽  
Jia Guo Zhu
Keyword(s):  
Integrated Circuits ◽  
Power Dissipation ◽  
Total Power ◽  
Cmos Process ◽  
Register File ◽  
Mos Transistors ◽  
Leakage Currents ◽  
Micro Power ◽  
Scaling Down ◽  
Threshold Technique

Scaling down sizes of MOS transistors has resulted in dramatic increase of leakage currents. The leakage dissipation caused by leakage currents is becoming an increasingly important fraction of the total power dissipation in nanometer integrated circuits. To decrease leakage power dissipations is becoming more and more important in micro-power nanometer circuits. An improved CAL register file using DTCMOS (Dual-Threshold Technique) for reducing leakage dissipations in active mode is addressed in this paper. The BSIM4 model is adopted to reflect the characteristics of the leakage currents. All circuits are simulated using HSPICE at 45nm CMOS process. Simulation results show that the register file with dual-threshold can reduce about 15.6% power dissipations.

Stress Induced Increased Low Level Leakage in Thin Oxides

1992 ◽  
Vol 284 ◽  
Author(s):  
D. J. Dumin ◽  
J. R. Maddux ◽  
D.-P. Wong
Keyword(s):  
Schottky Barrier ◽  
Stress Measurement ◽  
Tunneling Current ◽  
Schottky Emission ◽  
Leakage Currents ◽  
Gate Oxides ◽  
Low Level ◽  
Tunneling Currents ◽  
Best Fit ◽  
Nordheim Tunneling

ABSTRACTIt has been observed that the low-level, pre-tunneling currents through thin gate oxides increased after the oxides had been stressed at high voltages. The number of traps inside of the oxide generated by the stress has been shown to increase as the 1/3 power of the fluence that had passed through the oxide during the stress. The increases in the low-level, pre-tunneling currents have been shown to be proportional to the number of stress generated traps in the oxide and not to the fluence during the stress. The voltage dependences of the excess low-level leakage currents were stress and measurement polarity dependent. Attempts have been made to fit the voltage dependences of the excess low-level currents to Fowler-Nordheim tunneling, Frenkel-Poole conduction or Schottky barrier lowering. The increase in the portion of the low-level, pre-tunneling current that was not dependent on stress/measurement polarity sequence was best fit using Schottky emission currents. The model that has been developed to describe the increases in the low-level currents has centered on trap-assisted currents through the oxides.

Low Power Pulse-Triggered Flip-Flop Based on Clock Triggering Edge Control Technique

2015 ◽  
Vol 24 (07) ◽  
pp. 1550094 ◽  
Author(s):  
Jizhong Shen ◽  
Liang Geng ◽  
Xuexiang Wu
Keyword(s):  
Integrated Circuits ◽  
Power Dissipation ◽  
Energy Efficient ◽  
Clock Cycle ◽  
Control Technique ◽  
Switching Activity ◽  
Digital Integrated Circuits ◽  
Flip Flop ◽  
Deep Impact ◽  
Power Pulse

Flip-flop is an important unit in digital integrated circuits, whose characteristics have a deep impact on the performance of the circuits. To reduce the power dissipation of flip-flops, clock triggering edge control technique is proposed, which is feasible to block one or two triggering edges of a clock cycle if they are redundant in dual-edge pulse-triggered flip-flops (DEPFFs). Based on this technique, redundant pulses can be suppressed when the input stays unchanged, and all the redundant triggerings are eliminated to reduce redundant transitions at the internal nodes of the flip-flop, so the power dissipation can be decreased. Then a novel DEPFF based on clock triggering edge control (DEPFF-CEC) technique is proposed. Based on the SMIC 65-nm technology, the post layout simulation results show that the proposed DEPFF-CEC gains an improvement of 8.03–39.83% in terms of power dissipation when the input switching activity is 10%, as compared with its counterparts. Thus, it is suitable for energy-efficient designs whose input data switching activity is low.

APPLICATION OF EPITAXIAL UNIPOLAR BARRIERS TO REDUCE NOISE CURRENTS IN PHOTODETECTORS

2011 ◽  
Vol 20 (03) ◽  
pp. 557-564
Author(s):  
G. R. SAVICH ◽  
J. R. PEDRAZZANI ◽  
S. MAIMON ◽  
G. W. WICKS
Keyword(s):  
Leakage Current ◽  
Surface Passivation ◽  
Leakage Currents ◽  
Type Region ◽  
Surface Leakage Current ◽  
Unipolar Barrier ◽  
Trap Assisted Tunneling ◽  
Assisted Tunneling ◽  
Tunneling Currents ◽  
Surface Leakage

Tunneling currents and surface leakage currents are both contributors to the overall dark current which limits many semiconductor devices. Surface leakage current is generally controlled by applying a post-epitaxial passivation layer; however, surface passivation is often expensive and ineffective. Band-to-band and trap assisted tunneling currents cannot be controlled through surface passivants, thus an alternative means of control is necessary. Unipolar barriers, when appropriately applied to standard electronic device structures, can reduce the effects of both surface leakage and tunneling currents more easily and cost effectively than other methods, including surface passivation. Unipolar barriers are applied to the p -type region of a conventional, MBE grown, InAs based pn junction structures resulting in a reduction of surface leakage current. Placing the unipolar barrier in the n -type region of the device, has the added benefit of reducing trap assisted tunneling current as well as surface leakage currents. Conventional, InAs pn junctions are shown to exhibit surface leakage current while unipolar barrier photodiodes show no detectable surface currents.

Measurement of Fowler-Nordheim tunneling currents in MOS structures under charge trapping conditions

1985 ◽  
Vol 28 (7) ◽  
pp. 717-720 ◽  
Author(s):  
Y. Nissan-Cohen ◽  
J. Shappir ◽  
D. Frohman-Bentchkowsky
Keyword(s):  
Charge Trapping ◽  
Tunneling Currents ◽  
Mos Structures ◽  
Nordheim Tunneling

Electrothermal analysis of integrated circuits: a realization by infrared thermography

2021 ◽  
Author(s):  
Farnoos Farrokhi
Keyword(s):  
Temperature Distribution ◽  
Integrated Circuits ◽  
Power Dissipation ◽  
Electronic Device ◽  
Power Measurement ◽  
Device Under Test ◽  
Distribution Analysis ◽  
Ir Thermography ◽  
Temperature Dependent ◽  
Run Time

The International Technology Roadmap for Silicon (ITRS) predicted that by the year 2016, a high-performance chip could dissipate as much as 300 W/cm² of heat. Another more noticeable thermal issue in IC's is the uneven temperature distribution. Increased power dissipation and greater temperature variation highlight the need for electrothermal analysis of electronic components. The goal of this research is to develop an experimental infrared measurement technique for the thermal and electrothermal analysis of electronic circuits. The objective of the electrothermal analysis is to represent the behavior of the temperature dependent characteristics of electronic device in near real work condition. An infrared (IR) thermography setup to perform the temperature distribution analysis and power dissipation measurement of the device under test is proposed in this reasearch. The system is based on a transparent oil heatsink which captures the thermal profile and run-time power dissipation from the device under test with a very fine degree of granularity. The proposed setup is used to perform the thermal analysis and power measurement of an Intel Dual Core E2180 processor. The power dissipation of the processor is obtained by calculating and measuring the heat transfer coefficient of the oil heatsink. Moreover, the power consumption of the processor is measured by isolating the current used by the CPU at run time. A three-dimensional fininte element thermal model is developed to simulate the thermal properties of the processor. The results obtained using this simulation is compared to the experimental results from IR thermography. A methodology to perform electrothermal analysis on integrated circuits is introduced. This method is based on coupling a standard electrical simulator, which is often used in the design process, and IR thermography system through an efficient interface program. The proposed method is capable of updating the temperature dependent parameters of device in near real time. The proposed method is applied to perform electrothermal analysis of a power MOSFET to measure the temperature distribution and the device performance. The DC characteristics of the device are investigated. The obtained results indicated that the operating point, I-V characteristics and power dissipation of the MOSFET vary significantly with temperature.

scholarly journals A comparative study of hole and electron inversion layer quantization in MOS structures

2010 ◽  
Vol 7 (2) ◽  
pp. 185-193 ◽  
Author(s):  
Amit Chaudhry ◽  
Nath Roy
Keyword(s):  
Charge Density ◽  
Marked Decrease ◽  
Inversion Layer ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Gate Capacitance ◽  
Variation Approach ◽  
Inversion Charge ◽  
Mos Structures ◽  
Good Agreement

In this paper, an analytical model has been developed to study inversion layer quantization in nanoscale Metal Oxide Semiconductor Field Effect Oxide p-(MOSFET). n-MOSFETs have been studied using the variation approach and the p-MOSFETs have been studied using the triangular well approach. The inversion charge density and gate capacitance analysis for both types of transistors has been done. There is a marked decrease in the inversion charge density and the capacitance of the p-MOSFET as compared to n-MOSFETs. The results are compared with the numerical results showing good agreement.

Electrical Characteristics of Large Chip-Size 3.3 kV SiC-JBS Diodes

2013 ◽  
Vol 740-742 ◽  
pp. 881-886 ◽  
Author(s):  
Hiroyuki Okino ◽  
Norifumi Kameshiro ◽  
Kumiko Konishi ◽  
Naomi Inada ◽  
Kazuhiro Mochizuki ◽  
...  
Keyword(s):  
Electric Field ◽  
Schottky Barrier ◽  
Leakage Current ◽  
Reverse Current ◽  
Tunneling Current ◽  
Leakage Currents ◽  
Reverse Leakage Current ◽  
Low Leakage ◽  
Chip Size ◽  
Barrier Metal

The reduction of reverse leakage currents was attempted to fabricate 4H-SiC diodes with large current capacity for high voltage applications. Firstly diodes with Schottky metal of titanium (Ti) with active areas of 2.6 mm2 were fabricated to investigate the mechanisms of reverse leakage currents. The reverse current of a Ti Schottky barrier diode (SBD) is well explained by the tunneling current through the Schottky barrier. Then, the effects of Schottky barrier height and electric field on the reverse currents were investigated. The high Schottky barrier metal of nickel (Ni) effectively reduced the reverse leakage current to 2 x 10-3 times that of the Ti SBD. The suppression of the electric field at the Schottky junction by applying a junction barrier Schottky (JBS) structure reduced the reverse leakage current to 10-2 times that of the Ni SBD. JBS structure with high Schottky barrier metal of Ni was applied to fabricate large chip-size SiC diodes and we achieved 30 A- and 75 A-diodes with low leakage current and high breakdown voltage of 4 kV.

Conversion Tunneling in Non-Ideal Schottky Barriers: Virtual Resonance Manifestation and Interface States Influence

1996 ◽  
Vol 448 ◽  
Author(s):  
D.A. Romanov ◽  
A.V. Kalameitsev ◽  
A.P. Kovchavtsev ◽  
I.M. Subbotin
Keyword(s):  
Inversion Layer ◽  
Differential Resistance ◽  
Interface States ◽  
Tunnel Current ◽  
Semiconductor Interface ◽  
Near Surface ◽  
Electron States ◽  
Current Voltage ◽  
Transfer Matrix Approach ◽  
Mos Structures

AbstractWe have investigated experimentally and theoretically the elastic conversion tunneling of charge carriers in MOS structures Au on p+-InAs with superthin (10-20 Å) oxide film, the structures used in infrared photodetectors. In these structures the Schottky barrier provides near-surface inversion layer. The tunnel current-voltage (I-V) curves obtained at helium temperatures demonstrate the negative differential resistance region (NDR). We develop semiclassical two-band transfer matrix approach to the conversion tunneling analysis in a multilayer structure and calculate on its base the I-V curves dependence on the structure parameters. The NDR occurs to be caused by the motion of the remote quantum level in the inversion layer. The calculated I-V characteristics agree with the experimental ones quite well. The very existence of NDR and the shape of I-V curves depends strongly on the nature of localized electron states at the semiconductor interface. The characteristics of these electron states are used in the calculations as fitting parameters. Therefore, we suggest a new method for the interface states diagnosis.

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