Study on Dipole Layer Formation between Two Oxides : Experimental Evidences and Possible Models

2011 ◽  
Vol 1331 ◽  
Author(s):  
Koji Kita ◽  
Akira Toriumi
Keyword(s):  
Potential Barrier ◽  
Electric Potential ◽  
Driving Force ◽  
Areal Density ◽  
Density Difference ◽  
Layer Formation ◽  
Metal Insulator ◽  
Metal Insulator Semiconductor ◽  
Dipole Layer ◽  
Flatband Voltage

ABSTRACTHetero-interface between two oxides sometimes forms a dipole layer which is experimentally observable macroscopically, as an electric potential barrier at the interface. Investigation of the flatband voltage shift of the metal-insulator-semiconductor capacitors with bilayer oxides as the insulator is suitable to characterize the dipole formation at the interface of two oxides. A model to explain the driving force to form the dipole is discussed by taking account of the areal density difference of oxygen atoms at the interface, which should be a guideline to predict both the direction and magnitude of the interface dipoles. Based on this model the requirement for the oxides to form the dipoles is also discussed.

Abnormal Capacitance Hysteresis Phenomena in Stacked Nanocrystalline-Si Based Metal Insulator Semiconductor Memory Structure

2012 ◽  
Vol 531-532 ◽  
pp. 547-550
Author(s):  
Xiang Wang ◽  
Song Chao ◽  
Yan Qing Guo ◽  
Jie Song ◽  
Rui Huang
Keyword(s):  
Chemical Vapor ◽  
Memory Structure ◽  
Layer By Layer ◽  
Metal Insulator ◽  
Semiconductor Memory ◽  
Metal Insulator Semiconductor ◽  
Effect Model ◽  
Flatband Voltage ◽  
Hysteresis Phenomena ◽  
Nanocrystalline Si

Stack nanocrystalline-Si (nc-Si) based metal insulator semiconductor memory structure was fabricated by plasma enhanced chemical vapor deposition. The doubly stacked layers of nc-Si with the thickness of about 5 nm were fabricated by the layer-by-layer deposition technique with silane and hydrogen mixture gas. Capacitance-Voltage (C-V) measurements were used to investigate electron tunnel and storage characteristic. Abnormal capacitance hysteresis phenomena are obtained. The C-V results show that the flatband voltage increases at first, then decreases and finally increases, exhibiting a clear deep at gate voltage of 9 V. The charge transfer effect model was put forward to explain the electron storage and discharging mechanism of the stacked nc-Si based memory structure. The decreasing of flatband voltage at moderate programming bias is attributed to the transfer of electrons from the lower nc-Si layer to the upper nc-Si layer.

Traps in ZnS/Anodic Sulfide Film on Mercury Cadmium Telluride

1990 ◽  
Vol 216 ◽  
Author(s):  
S. Hikida ◽  
N. Kajihara ◽  
Y. Miyamoto
Keyword(s):  
Visible Light ◽  
Cadmium Telluride ◽  
Mercury Cadmium Telluride ◽  
Electron Trap ◽  
Semiconductor Diode ◽  
Trap Level ◽  
Metal Insulator ◽  
Metal Insulator Semiconductor ◽  
Sulfide Film ◽  
Flatband Voltage

ABSTRACTWe studied the influence of visible light on the ZnS/anodic sulfide/HgCdTe interface.We measured flatband voltage of metal-insulator-semiconductor diodes with semitransparent electrodes at 77 K. In the dark (i.e., without visible light). The flatband voltage of an metal-insulator-semiconductor diode is 0 V. We scanned visible light from 400 to 800 nm and measured the flatband voltage using the photocapacitance measurement. After an initial positive shift, the flatband voltage moved negative by as the wavelength shortened. We studied the relationship between the flatband voltage shift and photon energy using Fowler plots. Results suggest one electron trap level 1.5 eV above the valence band and two hole trap levels 1.7 and 2.3 eV below the conduction band.ZnS/anodic sulfide films on mercury cadmium telluride, studied using photoluminescence spectroscopy, showed broad photoluminescence peaks at 1.5, 1.7, and 2.3 eV, and the edge emission of the anodic sulfide.These results suggest that photoionization of the electron trap and two hole traps in the ZnS/anodic sulfide film causes the flatband shift.

Co-planar two-dimensional Metal-Insulator-Semiconductor Capacitor: Numerical study of the device electrostatics.

2017 ◽  
Author(s):  
Varun Bheemireddy
Keyword(s):  
Space Charge ◽  
High Performance ◽  
Numerical Study ◽  
2D Materials ◽  
Space Charge Density ◽  
Two Dimensional ◽  
Short Channel ◽  
Metal Insulator ◽  
Metal Insulator Semiconductor ◽  
New Family

The two-dimensional(2D) materials are highly promising candidates to realise elegant and e cient transistor. In the present letter, we conjecture a novel co-planar metal-insulator-semiconductor(MIS) device(capacitor) completely based on lateral 2D materials architecture and perform numerical study of the capacitor with a particular emphasis on its di erences with the conventional 3D MIS electrostatics. The space-charge density features a long charge-tail extending into the bulk of the semiconductor as opposed to the rapid decay in 3D capacitor. Equivalently, total space-charge and semiconductor capacitance densities are atleast an order of magnitude more in 2D semiconductor. In contrast to the bulk capacitor, expansion of maximum depletion width in 2D semiconductor is observed with increasing doping concentration due to lower electrostatic screening. The heuristic approach of performance analysis(2D vs 3D) for digital-logic transistor suggest higher ON-OFF current ratio in the long-channel limit even without third dimension and considerable room to maximise the performance of short-channel transistor. The present results could potentially trigger the exploration of new family of co-planar at transistors that could play a signi significant role in the future low-power and/or high performance electronics.<br>

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