Enhancement of Nonvolatile Floating Gate Memory Devices Containing AgInSbTe-SiO2 Nanocomposite by Inserting HfO2/SiO2 Blocking Oxide Layer

2011 ◽  
Vol 1337 ◽  
Author(s):  
Kuo-Chang Chiang ◽  
Tsung-Eong Hsieh
Keyword(s):  
Oxide Layer ◽  
Retention Time ◽  
Gate Voltage ◽  
Charge Trapping ◽  
Floating Gate ◽  
Voltage Sweep ◽  
Current Voltage ◽  
Charge Loss ◽  
Floating Gate Memory ◽  
Time Test

ABSTRACTThis work presents an enhancement of nonvolatile floating gate memory (NFGM) devices comprised of AgInSbTe (AIST) nanocomposite as the charge-storage trap layer and HfO2 or HfO2/SiO2 as the blocking oxide layer. A significantly large memory window (ΔVFB) shift = 30.7 V and storage charge density = 2.3×1013 cm−2 at ±23V gate voltage sweep were achieved in HfO2/SiO2/AIST sample. Retention time analysis observed a ΔVFB shift about 19.3 V and the charge loss about 13.4% in such a sample under the ±15V gate voltage stress after 104 sec retention time test. Regardless of applied bias direction, the sample containing HfO2/SiO2 layer exhibited the leakage current density as low as 150 nA/cm2 as revealed by the current-voltage (I-V) measurement. This effectively suppresses the electron injection between gate electrode and charge trapping layer and leads to a substantial enhancement of NFGM characteristics.

Nonvolatile Floating Gate Memory Devices Containing AgInSbTe-SiO2 Nanocomposite Thin Film Prepared by Sputtering Method

2010 ◽  
Vol 1250 ◽  
Author(s):  
Tsung-Eong Hsieh ◽  
Kuo-Chang Chiang
Keyword(s):  
Floating Gate ◽  
Cross Sectional ◽  
Nanocomposite Layer ◽  
Voltage Sweep ◽  
Charge Loss ◽  
Floating Gate Memory ◽  
Voltage Stress ◽  
Antimony Oxides ◽  
One Step ◽  
Time Test

AbstractAgInSbTe (AIST)-SiO2 nanocomposite layer prepared by a one-step sputtering process utilizing target-attachment method was implanted in the nonvolatile floating gate memory (NFGM) devices. Device sample subjected to post annealing at 400°C for 2 min in atmospheric ambient exhibited a significant hysteresis memory window (ΔVFB) shift = 5.91V and charge density = 5.22×12 cm-2 after ±8V voltage sweep. During the retention time test, a ΔVFB shift about 3.50 V and charge loss about 28.4% were observed in the sample after a ±5V voltage stress for 104 sec. Cross-sectional TEM revealed that the nanocomposite layer contains the crystalline AIST nanoparticles with the sizes about 5 to 7 nm embedded in SiO2 matrix. XPS analysis indicated that annealing induces the reduction of antimony oxides to form metallic Sb nanocrystals and suppresses the oxygen defects and charge loss in nanocomposite layer. Analytical results illustrated that the utilization of AIST-SiO2 nanocomposite layer may simplify the preparation of NFGM device with satisfactory electrical properties, implying a promising feasibility of such a nanocomposite layer to NFGM devices.

Influence of Embedded a-Si:H Layer Location on Floating-gate a-Si:H TFT Memory Functions

2010 ◽  
Vol 1245 ◽  
Author(s):  
Yue Kuo ◽  
Mary Coan
Keyword(s):  
Gate Voltage ◽  
Gate Dielectric ◽  
Dielectric Film ◽  
Memory Function ◽  
Charge Trapping ◽  
Floating Gate ◽  
Memory Functions ◽  
Voltage Sweep ◽  
Thin Channel ◽  
Large Memory

AbstractThe influence of the location of the embedded a-Si:H layer in the gate dielectric film of the floating-gate a-Si:H TFT on the charge trapping and detrapping mechanisms has been investigated. The thin channel-contact SiNx gate dielectric layer favors both hole and electron trappings under the proper gate voltage condition. The sweep gate voltage affect the locations and shapes of forward and backward transfer characteristics curves, which determines the memory function. In order to achieve a large memory window, both the location of the embedded a-Si:H layer and the gate voltage sweep range need to be optimized.

Organic field-effect transistor floating-gate memory using polysilicon as charge trapping layer

2019 ◽  
Vol 28 (8) ◽  
pp. 086801 ◽  
Author(s):  
Wen-Ting Zhang ◽  
Fen-Xia Wang ◽  
Yu-Miao Li ◽  
Xiao-Xing Guo ◽  
Jian-Hong Yang
Keyword(s):  
Field Effect ◽  
Field Effect Transistor ◽  
Charge Trapping ◽  
Floating Gate ◽  
Organic Field Effect Transistor ◽  
Floating Gate Memory ◽  
Effect Transistor

scholarly journals Effects of Charge Trapping at the MoS2–SiO2 Interface on the Stability of Subthreshold Swing of MoS2 Field Effect Transistors

Materials ◽  
2020 ◽  
Vol 13 (13) ◽  
pp. 2896 ◽  
Author(s):  
Xinnan Huang ◽  
Yao Yao ◽  
Songang Peng ◽  
Dayong Zhang ◽  
Jingyuan Shi ◽  
...  
Keyword(s):  
Gate Voltage ◽  
Field Effect ◽  
Field Effect Transistors ◽  
Charge Trapping ◽  
Interface States ◽  
Subthreshold Swing ◽  
Level Shift ◽  
Voltage Sweep ◽  
The Stability ◽  
Memory Applications

The stability of the subthreshold swing (SS) is quite important for switch and memory applications in logic circuits. The SS in our MoS2 field effect transistor (FET) is enlarged when the gate voltage sweep range expands towards the negative direction. This is quite different from other reported MoS2 FETs whose SS is almost constant while varying gate voltage sweep range. This anomalous SS enlargement can be attributed to interface states at the MoS2–SiO2 interface. Moreover, a deviation of SS from its linear relationship with temperature is found. We relate this deviation to two main reasons, the energetic distribution of interface states and Fermi level shift originated from the thermal activation. Our study may be helpful for the future modification of the MoS2 FET that is applied in the low power consumption devices and circuits.

CVD Growth and Passivation of W and TiN Nanocrystals for Non-volatile Memory Applications

2010 ◽  
Vol 1250 ◽  
Author(s):  
Guillaume Gay ◽  
Djamel Belhachemi ◽  
Jean-Philippe Colonna ◽  
Stéphane Minoret ◽  
Arnaud Beaurain ◽  
...  
Keyword(s):  
Silicon Nitride ◽  
Vapor Deposition ◽  
Chemical Vapor ◽  
Charge Trapping ◽  
Floating Gate ◽  
Chemical Vapor Deposition Growth ◽  
Floating Gate Memory ◽  
Non Volatile Memory ◽  
Cvd Growth ◽  
Memory Applications

AbstractIn this paper, we present CVD (Chemical Vapor Deposition) growth and passivation of tungsten (W) and titanium nitride (TiN) nanocrystals (NCs) on silicon dioxide and silicon nitride for use as charge trapping layer in floating gate memory devices. NCs are deposited in an 8 inches industrial CVD Centura tool. W and TiN are chosen for being compatible with MOSFET memory fabrication process. For protecting NCs from oxidation, a silicon shell is selectively deposited on them. Moreover, for a better passivation, TiN NCs are encapsulated in silicon nitride (Si3N4) in order to get rid of oxidation issues. After high temperature annealing (1050°C under N2 during 1 minute) XPS measurements point out that NCs are still metallic, which makes them good candidates for being used as charge trapping layer in floating gate memories.

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