Low-Cost Wafer-Level Vacuum Packaging for MEMS

MRS Bulletin ◽  
2003 ◽  
Vol 28 (1) ◽  
pp. 55-59 ◽  
Author(s):  
Roland Gooch ◽  
Thomas Schimert
Keyword(s):  
Microelectromechanical Systems ◽  
Infrared Imaging ◽  
Rf Mems ◽  
Low Cost ◽  
Vacuum Packaging ◽  
Product Line ◽  
Focal Plane Arrays ◽  
Wafer Level ◽  
Component Level ◽  
Widespread Application

AbstractVacuum packaging of high-performance surface-micromachined uncooled microbolometer detectors and focal-plane arrays (FPAs) for infrared imaging and nonimaging applications, inertial MEMS (microelectromechanical systems) accelerometers and gyroscopes, and rf MEMS resonators is a key issue in the technology development path to low-cost, high-volume MEMS production. In this article, two approaches to vacuum packaging for MEMS will be discussed. The first is component-level vacuum packaging, a die-level approach that involves packaging individual die in a ceramic package using either a silicon or germanium lid. The second approach is wafer-level vacuum packaging, in which the vacuum-packaging process is carried out at the wafer level prior to dicing the wafer into individual die. We focus the discussion of MEMS vacuum packaging on surface-micromachined uncooled amorphous silicon infrared microbolometer detectors and FPAs for which both component-level and wafer-level vacuum packaging have found widespread application and system insertion. We first discuss the requirement for vacuum packaging of uncooled a-Si microbolometers and FPAs. Second, we discuss the details of the component-level and wafer-level vacuum-packaging approaches. Finally, we discuss the system insertion of wafer-level vacuum packaging into the Raytheon 2000AS uncooled infrared imaging camera product line that employs a wafer-level-packaged 160 × 120 pixel a-Si infrared FPA.

RF-MEMS Components and Networks for High-Performance Reconfigurable Telecommunication and Wireless Systems

2012 ◽  
Vol 81 ◽  
pp. 65-74 ◽  
Author(s):  
Jacopo Iannacci ◽  
Giuseppe Resta ◽  
Paola Farinelli ◽  
Roberto Sorrentino
Keyword(s):  
High Performance ◽  
Microelectromechanical Systems ◽  
Rf Mems ◽  
Low Cost ◽  
Impedance Matching ◽  
Phase Shifters ◽  
Rf Systems ◽  
Mems Technology ◽  
And Performance ◽  
Rf Performance

MEMS (MicroElectroMechanical-Systems) technology applied to the field of Radio Frequency systems (i.e. RF-MEMS) has emerged in the last 10-15 years as a valuable and viable solution to manufacture low-cost and very high-performance passive components, like variable capacitors, inductors and micro-relays, as well as complex networks, like tunable filters, reconfigurable impedance matching networks and phase shifters, and so on. The availability of such components and their integration within RF systems (e.g. radio transceivers, radars, satellites, etc.) enables boosting the characteristics and performance of telecommunication systems, addressing for instance a significant increase of their reconfigurability. The benefits resulting from the employment of RF-MEMS technology are paramount, being some of them the reduction of hardware redundancy and power consumption, along with the operability of the same RF system according to multiple standards. After framing more in detail the whole context of RF MEMS technology, this paper will provide a brief introduction on a typical RF-MEMS technology platform. Subsequently, some relevant examples of lumped RF MEMS passive elements and complex reconfigurable networks will be reported along with their measured RF performance and characteristics.

Application of SU-8 photoresist as a multi-functional structural dielectric layer in FOWLP

2017 ◽  
Vol 2017 (DPC) ◽  
pp. 1-19
Author(s):  
Raquel Pinto ◽  
André Cardoso ◽  
Sara Ribeiro ◽  
Carlos Brandão ◽  
João Gaspar ◽  
...  
Keyword(s):  
Structural Material ◽  
High Performance ◽  
Microelectromechanical Systems ◽  
Low Cost ◽  
Process Conditions ◽  
Processing Temperature ◽  
Wafer Level ◽  
Fast Growing ◽  
Wide Range ◽  
Different Types

Microelectromechanical Systems (MEMS) are a fast growing technology for sensor and actuator miniaturization finding more and more commercial opportunities by having an important role in the field of Internet of Things (IoT). On the same note, Fan-out Wafer Level Packaging (FOWLP), namely WLFO technology of NANIUM, which is based on Infineon/ Intel eWLB technology, is also finding further applications, not only due to its high performance, low cost, high flexibility, but also due to its versatility to allow the integration of different types of components in the same small form-factor package. Despite its great potential it is still off limits to the more sensitive components as micro-mechanical devices and some type of sensors, which are vulnerable to temperature and pressure. In the interest of increasing FOWLP versatility and enabling the integration of MEMS, new methods of assembling and processing are continuously searched for. Dielectrics currently used for redistribution layer construction need to be cured at temperatures above 200°C, making it one of the major boundary for low temperature processing. In addition, in order to accomplish a wide range of dielectric thicknesses in the same package it is often necessary to stack very different types of dielectrics with impact on bill of materials complexity and cost. In this work, done in cooperation with the International Iberian Nanotechnology Laboratory (INL), we describe the implementation of commercially available SU-8 photoresist as a structural material in FOWLP, allowing lower processing temperature and reduced internal package stress, thus enabling the integration of components such as MEMS/MOEMS, magneto-resistive devices and micro-batteries. While SU-8 photoresist was first designed for the microelectronics industry, it is currently highly used in the fabrication of microfluidics as well as microelectromechanical systems (MEMS) and BIO-MEMS due to its high biocompatibility and wide range of available thicknesses in the same product family. Its good thermal and chemical resistance and also mechanical and rheological properties, make it suitable to be used as a structural material, and moreover it cures at 150°C, which is key for the applications targeted. Unprecedentedly, SU-8 photoresist is tested in this work as a structural dielectric for the redistribution layers on 300mm fan-out wafers. Main concerns during the evaluation of the new WLFO dielectric focused on processability quality; adhesion to multi-material substrate and metals (copper, aluminium, gold, ¦); between layers of very different thicknesses; and overall reliability. During preliminary runs, processability on 300 mm fan-out wafers was evaluated by testing different coating and soft bake conditions, exposure settings, post-exposure parameters, up to developing setup. The outputs are not only on process conditions and results but also on WLFO design rules. For the first time, a set of conditions has been defined that allows processing SU-8 on WLFO, with thickness values ranging from 1 um to 150 um. The introduction of SU-8 in WLFO is a breakthrough in this fast-growing advanced packaging technology platform as it opens vast opportunities for sensor integration in WLP technology.

Creating Semiconductor Value through Advanced Package Technology

2016 ◽  
Vol 2016 (S1) ◽  
pp. S1-S46
Author(s):  
Ron Huemoeller
Keyword(s):  
Big Five ◽  
Flip Chip ◽  
Microelectromechanical Systems ◽  
Technology Innovation ◽  
Low Cost ◽  
Semiconductor Industry ◽  
Significant Shift ◽  
Wafer Level ◽  
Chip Scale Package ◽  
Advanced Packaging

Over the past few years, there has been a significant shift from PCs and notebooks to smartphones and tablets as drivers of advanced packaging innovation. In fact, the overall packaging industry is doing quite well today as a result, with solid growth expected to create a market value in excess of $30B USD by 2020. This is largely due to the technology innovation in the semiconductor industry continuing to march forward at an incredible pace, with silicon advancements in new node technologies continuing on one end of the spectrum and innovative packaging solutions coming forward on the other in a complementary fashion. The pace of innovation has quickened as has the investments required to bring such technologies to production. At the packaging level, the investments required to support the advancements in silicon miniaturization and heterogeneous integration have now reached well beyond $500M USD per year. Why has the investment to support technology innovation in the packaging community grown so much? One needs to look no further than the complexity of the most advanced package technologies being used today and coming into production over the next year. Advanced packaging technologies have increased in complexity over the years, transitioning from single to multi-die packaging, enabled by 3-dimensional integration, system-in-package (SiP), wafer-level packaging (WLP), 2.5D/3D technologies and creative approached to embedding die. These new innovative packaging technologies enable more functionality and offer higher levels of integration within the same package footprint, or even more so, in an intensely reduced footprint. In an industry segment that has grown accustomed to a multitude of package options, technology consolidation seems evident, producing “The Big Five” advanced packaging platforms. These include low-cost flip chip, wafer-level chip-scale package (WLCSP), microelectromechanical systems (MEMS), laminate-based advanced system-in-package (SiP) and wafer-based advanced SiP designs. This presentation will address ‘The Big Five’ packaging platforms and how they are adding value to the Semiconductor Industry.

Very large scale heterogeneous integration (VLSHI) and wafer-level vacuum packaging for infrared bolometer focal plane arrays

2013 ◽  
Vol 60 ◽  
pp. 251-259 ◽  
Author(s):  
Fredrik Forsberg ◽  
Niclas Roxhed ◽  
Andreas C. Fischer ◽  
Björn Samel ◽  
Per Ericsson ◽  
...  
Keyword(s):  
Focal Plane ◽  
Large Scale ◽  
Vacuum Packaging ◽  
Focal Plane Arrays ◽  
Heterogeneous Integration ◽  
Wafer Level

Micro/Nanotribology of RF MEMS Switches

2004 ◽  
Author(s):  
Steven T. Patton ◽  
Kalathil C. Eapen ◽  
Jeffrey S. Zabinski
Keyword(s):  
Electric Current ◽  
Microelectromechanical Systems ◽  
Rf Mems ◽  
Low Cost ◽  
Operating Conditions ◽  
Great Promise ◽  
Rf Switches ◽  
Mems Switches ◽  
Adhesion Contact ◽  
Rf Mems Switches

Microelectromechanical systems (MEMS) radio frequency (RF) switches hold great promise in a myriad of commercial, aerospace, and military applications. MEMS switches offer important advantages over current electromechanical and solid state technologies including high linearity, low insertion loss, low power consumption, good isolation, and low cost [1–21]. However, there is little fundamental understanding of the factors determining the performance and reliability of these devices. Our previous work investigated fundamentals of hot-switched direct current (DC) gold (Au) contacts using a modified microadhesion apparatus as a switch simulator [1]. Those experiments were conducted under precisely controlled operating conditions in air at MEMS-scale forces with an emphasis on the role of surface forces and electric current on switch performance, reliability, and durability [1]. Electric current had a profound effect on deformation mechanisms, adhesion, contact resistance (R), and reliability/durability. At low current (1–10 μA), asperity creep and switching induced adhesion were the most important observations, whereas, at high current (1–10 mA), lack of adhesion and switch shorting by nanowire formation were prominent [1].

Next Generation eWLB (Embedded Wafer Level BGA): Advanced 3D SiP Packaging Solution

2012 ◽  
Vol 2012 (DPC) ◽  
pp. 001507-001526 ◽  
Author(s):  
Seung Wook Yoon ◽  
Yaojian Lin ◽  
Yonggang Jin ◽  
Jerome Teysseyre ◽  
Xavier Baraton ◽  
...  
Keyword(s):  
Low Cost ◽  
Standard Test ◽  
Structural Defects ◽  
Special Focus ◽  
Next Generation ◽  
Wafer Level ◽  
Process Technology ◽  
Component Level ◽  
Chip Area ◽  
Board Level

Current and future demands of mobile/portable electronic systems in terms of performance, power consumption, reliable system at a reasonable price are met by developing advanced/appropriate silicon process technology, innovative packaging solutions with use of chip-package-system co-design, low cost materials, advanced assembly and reliable interconnect technologies. In this article packaging evolution for hand held application is discussed with special focus on next generation chip embedding technology called eWLB in detail. To meet the above said challenges eWLB was developed which offers additional space for routing higher I/O chips on top of Silicon chip area which is not possible in conventional WLP or WLB. It also offers comparatively better electrical, thermal and reliability performance at reduced cost with possibility to address more Moore [decreasing technology nodes with low-k dielectrics in SoC] and more than Moore [heterogeneous integration of chips with different wafer technology as SiP solution in multi die or 3D eWLB approaches]. Currently 1st generation eWLB technology is available in the industry with 200mm and 300mm carrier size. This paper will highlight some of the recent advancements in progress development and mechnical characterization in component level and board level reliaiblity of next generation eWLB technologies of double-side 3D eWLB. Standard JEDEC tests were carried out to investigate component level reliability and both destructive/non-destructive analysis was performed to investigate potential structural defects. Daisychain Test vehicles were prepared and also tested for drop and TcoB (Temperature on Board) reliaiblity in industry standard test conditions. There was significant improvement of characteristic lifetime with thined eWLB in TcoB performance because of its enhanced flexibility of package. And there was study of board level reliabiilty with underfill in SMT for large size eWLB packages. This paper will also present study of package warpage behavior with temperature profile as well as failure analysis with microsturctural observation for comprehensive understanding of mechanical behavior of next generation eWLBs.

RF MEMS Switch Heat Dissipation in Discrete and Wafer-Level MEMS Packages

2002 ◽  
Author(s):  
Lei L. Mercado ◽  
Tien-Yu Tom Lee ◽  
Shun-Meen Kuo ◽  
Vern Hause ◽  
Craig Amrine
Keyword(s):  
Power Density ◽  
Contact Area ◽  
Heat Dissipation ◽  
Microelectromechanical Systems ◽  
Rf Mems ◽  
Material Selection ◽  
Junction Temperature ◽  
Mems Devices ◽  
Wafer Level ◽  
Die Attach

In discrete RF (Radio Frequency) MEMS (MicroElectroMechanical Systems) packages, MEMS devices were fabricated on Silicon or GaAs (Galium Arsenide) chips. The chips were then attached to substrates with die attach materials. In wafer-level MEMS packages, the switches were manufactured directly on substrates. For both types of packages, when the switches close, a contact resistance of approximately 1 Ohm exists at the contact area. As a result, during switch operations, a considerable amount of heat is generated in the minuscule contact area. The power density at the contact area could be up to 1000 times higher than that of typical power amplifiers. The high power density may overheat the contact area, therefore affect switch performance and jeopardize long-term switch reliabilities. In this paper, thermal analysis was performed to study the heat dissipation at the switch contact area. The goal is to control the “hot spots” and lower the maximum junction temperature at the contact area. A variety of chip materials, including Silicon, GaAs have been evaluated for the discrete packages. For each chip material, the effect of die attach materials was considered. For the wafer-level packages, various substrate materials, such as ceramic, glass, and LTCC (Low-Temperature Cofire Ceramic) were studied. Thermal experiments were conducted to measure the temperature at the contact area and its vicinity as a function of DC and RF powers. Several solutions in material selection and package configurations were explored to enable the use of MEMS with chips or substrates with relatively poor thermal conductivity.

Advances in the Fabrication Processes and Applications of Wafer Level Packaging

2014 ◽  
Vol 136 (2) ◽  
Author(s):  
Peisheng Liu ◽  
Jinlan Wang ◽  
Liangyu Tong ◽  
Yujuan Tao
Keyword(s):  
Integrated Circuit ◽  
Microelectromechanical Systems ◽  
Low Cost ◽  
Electrical Performance ◽  
Wafer Level ◽  
Wafer Level Packaging ◽  
3D Packaging ◽  
Circuit Fabrication ◽  
Fast Development ◽  
Small Form Factor

Fast development of wafer level packaging (WLP) in recent years is mainly owing to the advances in integrated circuit fabrication process and the market demands for devices with high electrical performance, small form factor, low cost etc. This paper reviews the advances of WLP technology in recent years. An overall introduction to WLP is presented in the first part. The fabrication processes of WLP and redistribution technology are introduced in the second part. Reliability problems of WLPs, such as the strength of solder joints and reliability problems concerning fan-out WLPs are introduced in the third part. Typical applications of WLP technologies are discussed in the last part, which include the application of fan-out WLP, 3D packaging integrating with WLP technologies and its application in microelectromechanical systems (MEMS).

The low-complexity RF MEMS switch at EADS: an overview

2011 ◽  
Vol 3 (5) ◽  
pp. 499-508 ◽  
Author(s):  
Bernhard Schoenlinner ◽  
Armin Stehle ◽  
Christian Siegel ◽  
William Gautier ◽  
Benedikt Schulte ◽  
...  
Keyword(s):  
Microelectromechanical Systems ◽  
Silicon Oxide ◽  
Rf Mems ◽  
Low Cost ◽  
Low Complexity ◽  
Phase Shifters ◽  
Experimental Investigations ◽  
Rf Mems Switch ◽  
Capacitive Switch ◽  
Mems Switch

This paper gives an overview of the low-complexity radio frequency microelectromechanical systems (RF MEMS) switch concept and technology of EADS Innovation Works in Germany. Starting in 2003, a capacitive switch concept, which is unique in several aspects, was developed to address specific needs in the aeronautic and space. Thermally grown silicon oxide as dielectric layer, the silicon substrate as actuation electrode, and a conductive zone realized by ion implantation make the EADS RF MEMS switch a very simple, low-cost, and reliable approach. In this document, data on experimental investigations are presented, which demonstrate outstanding performance figures in terms of insertion loss, isolation, frequency range, bandwidth, RF-power handling, and robustness with respect to thermal load. Based on this concept, numerous different circuits in particular single-pole single-throws (SPSTs), single-pole multi-throws (SPMTs), tunable filters, phase shifters, and electronically steerable antennas between 6 and 100 GHz have been designed, fabricated, and characterized.

Low Cost Microbolometer Development Using Commercially Available CMOS Foundry Processes

2002 ◽  
Author(s):  
Khoa V. Dang ◽  
Philippe Pouliquen ◽  
Michael Grenn ◽  
Andreas Andreou ◽  
Paul Blase ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Infrared Imaging ◽  
Low Cost ◽  
Cost Effective ◽  
Focal Plane Arrays ◽  
Production Costs ◽  
Cmos Process ◽  
Test Results ◽  
Uncooled Microbolometer ◽  
Dry Etch

We have demonstrated the monolithic fabrication of uncooled microbolometer Focal Plane Arrays (FPAs) for infrared imaging applications using available CMOS, BiCMOS foundry processing and micromachining techniques which trade higher performance with potentially much higher yield and lower production costs. Past and current efforts have exclusively focused on using the commercial silicon foundries for the Readout Integrated Circuits (ROICs) fabrication, and then the microbolometer detector bridges are fabricated on top of the ROICs using processes that involve many complex growth layers and etching steps. These current approaches require specialized microbolometer fabrication facilities and foundries to be built and maintained. We have demonstrated methods to fabricate inexpensive, reasonable performance uncooled microbolometer FPAs using commercially available silicon foundries. To be truly cost effective, we are using the commercial foundries to fabricate the microbolometer FPAs. To release or suspend the bolometer structures, we have used a simple post-foundry maskless anisostropic or isotropic wet/dry etch. We have fabricated a prototype 13×14 uncooled microbolometer FPA using the commercial AMI 1.5um CMOS process as well as a 38×38 microbolometer array using the AMI 0.5um CMOS process. Discussions of the microbolometer circuit designs, MEMS micromachining techniques, and test results will be presented.

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