Packaging Options for MEMS Devices

MRS Bulletin ◽  
2003 ◽  
Vol 28 (1) ◽  
pp. 51-54 ◽  
Author(s):  
Erik Jung
Keyword(s):  
Integrated Circuit ◽  
Microelectromechanical Systems ◽  
Mems Devices ◽  
Single Chip ◽  
Wafer Level ◽  
Product Failure ◽  
Product Success ◽  
Microelectronics Industry ◽  
The Right ◽  
Crucial Part

AbstractMicroelectromechanical systems (MEMS) devices can be delicate structures sensitive to damage from handling or environmental influences. Their functionality may furthermore depend on sealing out the environment or being in direct contact with it. Stress, thermal load, and contaminants may change their characteristics. Here, packaging technology is challenged to extend from microelectronics toward MEMS and optoelectronic MEMS (MOEMS). Today's approaches rely on modified single-chip packages derived from the microelectronics industry, wafer-level capping to enable the device to be packaged like an integrated circuit, or highly specialized packages designed to complement the function of the MEMS device itself. Selecting the proper packaging method may tip the scale toward a product success or a product failure. Choosing the right technology, therefore, is a crucial part of the product design.

Microsensors, MEMS and NEMS Based Complex Adaptive Smart Devices and Systems

2001 ◽  
Author(s):  
Vijay K. Varadan
Keyword(s):  
Self Assembly ◽  
Communication Systems ◽  
Microelectromechanical Systems ◽  
System Level ◽  
Smart Devices ◽  
Mems Devices ◽  
Wafer Level ◽  
Sensors And Actuators ◽  
Complex Adaptive ◽  
Microelectronics Industry

Abstract The microelectronics industry has seen explosive growth during the last thirty years. Extremely large markets for logic and memory devices have driven the development of new materials, and technologies for the fabrication of even more complex devices with features sizes now down at the sub micron level. Recent interest has arisen in employing these materials, tools and technologies for the fabrication of miniature sensors and actuators and their integration with electronic circuits to produce smart devices and MicroElectroMechanical Systems (MEMS). This effort offers the promise of: 1. Increasing the performance and manufacturability of both sensors and actuators by exploiting new batch fabrication processes developed for the IC and microelectronics industry. Examples include micro stereo lithographic and micro molding techniques. 2. Developing novel classes of materials and mechanical structures not possible previously, such as diamond like carbon, silicon carbide and carbon nanotubes, micro-turbines and micro-engines. 3. Development of technologies for the system level and wafer level integration of micro components at the nanometer precision, such as self-assembly techniques and robotic manipulation. 4. Development of control and communication systems for MEMS devices, such as optical and RF wireless, and power delivery systems.

A System for Electromechanical Reliability Testing of MEMS Devices

2006 ◽  
Author(s):  
Stefan Spinner ◽  
Michael Doelle ◽  
Patrick Ruther ◽  
Oliver Paul ◽  
Ilia Polian ◽  
...  
Keyword(s):  
Mechanical Stress ◽  
Microelectromechanical Systems ◽  
Automated Analysis ◽  
Dynamic Loads ◽  
Reliability Testing ◽  
Mems Devices ◽  
Single Chip ◽  
Wafer Level ◽  
Optical Inspection

Abstract This paper reports on a setup and a method that enables automated analysis of mechanical stress impact on microelectromechanical systems (MEMS). In this setup both electrical and optical inspection are available. Reliability testing is possible on a single chip as well as on the wafer level. Mechanical stress is applied to the tested structure with programmable static forces up to 3.6 N and dynamic loads at frequencies up to 20 Hz. The applications of the presented system include the postmanufacturing test, characterization and stress screens as well as reliability studies. We report preliminary results of long-term reliability testing obtained for a CMOS-based stress sensor.

Wafer-Level Strength and Fracture Toughness Testing of Surface-Micromachined MEMS Devices

1999 ◽  
Vol 605 ◽  
Author(s):  
H. Kahn ◽  
N. Tayebi ◽  
R. Ballarini ◽  
R.L. Mullen ◽  
A.H. Heuer
Keyword(s):  
Fracture Toughness ◽  
Tensile Strength ◽  
Microelectromechanical Systems ◽  
Reliability Prediction ◽  
Bend Strength ◽  
Mems Devices ◽  
Wafer Level ◽  
Toughness Testing ◽  
Loading Devices

AbstractDetermination of the mechanical properties of MEMS (microelectromechanical systems) materials is necessary for accurate device design and reliability prediction. This is most unambiguously performed using MEMS-fabricated test specimens and MEMS loading devices. We describe here a wafer-level technique for measuring the bend strength, fracture toughness, and tensile strength of MEMS materials. The bend strengths of surface-micromachined polysilicon, amorphous silicon, and polycrystalline 3C SiC are 5.1±1.0, 10.1±2.0, and 9.0±1.0 GPa, respectively. The fracture toughness of undoped and P-doped polysilicon is 1.2±0.2 MPa√m, and the tensile strength of polycrystalline 3C SiC is 3.2±1.2 GPa. These results include the first report of the mechanical strength of micromachined polycrystalline 3C SiC.

scholarly journals Selective W for Coating and Releasing MEMS Devices

1999 ◽  
Vol 605 ◽  
Author(s):  
S. S. Mani ◽  
J. G. Fleming ◽  
J. J. Sniegowski ◽  
M. P. de Boer ◽  
L. W. Irwin ◽  
...  
Keyword(s):  
Integrated Circuit ◽  
Microelectromechanical Systems ◽  
Process Integration ◽  
Chemical Vapor ◽  
Deposition Process ◽  
Tungsten Coating ◽  
Mems Devices ◽  
Selective Deposition ◽  
Small Areas ◽  
Conformal Coating

AbstractTwo major problems associated with Si-based MEMS (MicroElectroMechanical Systems) devices are stiction and wear. Surface modifications are needed to reduce both adhesion and friction in micromechanical structures to solve these problems. In this paper, we will present a CVD (Chemical Vapor Deposition) process that selectively coats MEMS devices with tungsten and significantly enhances device durability. Tungsten CVD is used in the integrated-circuit industry, which makes this approach manufacturable. This selective deposition process results in a very conformal coating and can potentially address both stiction and wear problems confronting MEMS processing. The selective deposition of tungsten is accomplished through the silicon reduction of WF6. The self-limiting nature of this selective W deposition process ensures the consistency necessary for process control. The tungsten is deposited after the removal of the sacrificial oxides to minimize stress and process integration problems. Tungsten coating adheres well and is hard and conducting, requirements for device performance. Furthermore, since the deposited tungsten infiltrates under adhered silicon parts and the volume of W deposited is less than the amount of Si consumed, it appears to be possible to release stuck parts that are contacted over small areas such as dimples. The wear resistance of selectively coated W parts has been shown to be significantly improved on microengine test structures.

Advanced Packaging for Automotive Dashboard Application

2017 ◽  
Vol 2017 (DPC) ◽  
pp. 1-26
Author(s):  
Nokibul Islam
Keyword(s):  
Integrated Circuit ◽  
High Performance ◽  
Flip Chip ◽  
Wafer Level ◽  
Automotive Market ◽  
Performance Requirements ◽  
Advanced Packaging ◽  
Packaging Industry ◽  
The Right ◽  
Board Level

The current automotive market for the IC (integrated circuit) packaging industry has grown significantly due to the increasing need for automation and higher performance in vehicles. These changes in the automotive market will enable cars to be more reliable and intelligent. To address the increasingly complex demands of the automotive market, the semiconductor packaging industry is shifting its focus to prioritize the development of advanced packages for next generation automotive market requirements. Automotive IC's are traditionally wirebond packages. Due to the increasing complexity and higher performance requirements of automotive applications, the packaging industry is moving towards high performance flip chip packages for automotive infotainment, GPS, and radar applications. In this study a comprehensive view of the changing packaging landscape from traditional wirebond to flip chip interconnect to advanced fan-out wafer level packages will be discussed. The pros and cons of each packaging technology will be examined Packaging roadmap details will be discussed along with assembly process information, determining the right BOM (bill of materials), cost data, and extensive package and board level reliability.

RF MEMS Switch Heat Dissipation in Discrete and Wafer-Level MEMS Packages

2002 ◽  
Author(s):  
Lei L. Mercado ◽  
Tien-Yu Tom Lee ◽  
Shun-Meen Kuo ◽  
Vern Hause ◽  
Craig Amrine
Keyword(s):  
Power Density ◽  
Contact Area ◽  
Heat Dissipation ◽  
Microelectromechanical Systems ◽  
Rf Mems ◽  
Material Selection ◽  
Junction Temperature ◽  
Mems Devices ◽  
Wafer Level ◽  
Die Attach

In discrete RF (Radio Frequency) MEMS (MicroElectroMechanical Systems) packages, MEMS devices were fabricated on Silicon or GaAs (Galium Arsenide) chips. The chips were then attached to substrates with die attach materials. In wafer-level MEMS packages, the switches were manufactured directly on substrates. For both types of packages, when the switches close, a contact resistance of approximately 1 Ohm exists at the contact area. As a result, during switch operations, a considerable amount of heat is generated in the minuscule contact area. The power density at the contact area could be up to 1000 times higher than that of typical power amplifiers. The high power density may overheat the contact area, therefore affect switch performance and jeopardize long-term switch reliabilities. In this paper, thermal analysis was performed to study the heat dissipation at the switch contact area. The goal is to control the “hot spots” and lower the maximum junction temperature at the contact area. A variety of chip materials, including Silicon, GaAs have been evaluated for the discrete packages. For each chip material, the effect of die attach materials was considered. For the wafer-level packages, various substrate materials, such as ceramic, glass, and LTCC (Low-Temperature Cofire Ceramic) were studied. Thermal experiments were conducted to measure the temperature at the contact area and its vicinity as a function of DC and RF powers. Several solutions in material selection and package configurations were explored to enable the use of MEMS with chips or substrates with relatively poor thermal conductivity.

Advances in the Fabrication Processes and Applications of Wafer Level Packaging

2014 ◽  
Vol 136 (2) ◽  
Author(s):  
Peisheng Liu ◽  
Jinlan Wang ◽  
Liangyu Tong ◽  
Yujuan Tao
Keyword(s):  
Integrated Circuit ◽  
Microelectromechanical Systems ◽  
Low Cost ◽  
Electrical Performance ◽  
Wafer Level ◽  
Wafer Level Packaging ◽  
3D Packaging ◽  
Circuit Fabrication ◽  
Fast Development ◽  
Small Form Factor

Fast development of wafer level packaging (WLP) in recent years is mainly owing to the advances in integrated circuit fabrication process and the market demands for devices with high electrical performance, small form factor, low cost etc. This paper reviews the advances of WLP technology in recent years. An overall introduction to WLP is presented in the first part. The fabrication processes of WLP and redistribution technology are introduced in the second part. Reliability problems of WLPs, such as the strength of solder joints and reliability problems concerning fan-out WLPs are introduced in the third part. Typical applications of WLP technologies are discussed in the last part, which include the application of fan-out WLP, 3D packaging integrating with WLP technologies and its application in microelectromechanical systems (MEMS).

Microelectromechanical Systems Cantilever Resonators: Pressure-Dependent Gas Film Damping

2020 ◽  
Vol 142 (9) ◽  
Author(s):  
Chu Rainer Kwang-Hua
Keyword(s):  
Quality Factor ◽  
Knudsen Number ◽  
Microelectromechanical Systems ◽  
Unit Length ◽  
Mems Devices ◽  
Dynamical Friction ◽  
Quality Factors ◽  
Wafer Level ◽  
Unsteady Fluid ◽  
Parameter Per Unit Length

Abstract Under near-vacuum conditions, the fluid frictional dissipation or approximately the inverse of the quality factor of a microcantilever once the intrinsic dissipation can be neglected is proportional to the low pressure. We shall investigate the dynamic behavior of micro-electromechanical systems (MEMS) devices via the calculation of the quality factor or frictional damping forces resulting from surrounding gases. Here, we illustrated some specific examples relevant to the computation of the quality factor or dynamical friction for an oscillating microcantilever in air via measurements of the paper of Okada et al. (Okada, H., Itoh, T., and Suga, T., 2008, Wafer Level Sealing Characterization Method Using Si Micro Cantilevers,” Sens. Actuators A, 147(2), pp. 359–364) considering the quality factors of the CM (a label for a microcantilever: 500 × 90 × 5 μm3 Si microcantilever (the measured resonance frequency: 23.7 kHz) and the paper of Kara et al. (Kara, V., Yakhot, V., and Ekinci, K. L., 2017, Generalized Knudsen Number for Unsteady Fluid Flow, Phys. Rev. Lett., 118(7), p. 074505) in rarefied gases regime. We present the corrected quality factor or dynamical friction over the whole range of the Knudsen number considering the CM part by Okada et al. Our new plot considering the quality factor which is proportional to the inverse of the dissipative friction parameter per unit length, pressure as well as the Knudsen number over the whole range should be useful to researchers in this field.

Mechanics of Direct Wafer Bonding

2003 ◽  
Author(s):  
K. T. Turner ◽  
S. M. Spearing
Keyword(s):  
Wafer Bonding ◽  
Microelectromechanical Systems ◽  
Surface Condition ◽  
Bonding Process ◽  
Mems Devices ◽  
Wafer Level ◽  
Modeling Framework ◽  
Etch Patterns ◽  
Direct Wafer Bonding ◽  
Bonding Failure

Direct wafer bonding, also known as fusion bonding, has emerged as a key process in the manufacture of microelectromechanical systems (MEMS). The use of wafer bonding increases design flexibility, allows integration of dissimilar materials, and permits wafer-level packaging. While direct wafer bonding processes are becoming more prevalent in the fabrication of MEMS devices, failure during the bonding process is often a problem and is not completely understood. A modeling framework, based on the mechanics of the bonding process, has been on the mechanics of the bonding process, has been developed to correlate bonding failure to wafer geometry, surface condition, and etch patterns. The modeling approach is based on an energy balance between the reduction in surface energy as the bond is formed and the strain energy that is stored in the wafers as they conform to each other. The model allows the effect of flatness deviations, wafer geometry (i.e. thickness, diameter), wafer mounting, and etched features on the bonding process to be shown. Modeling results demonstrate that wafer bow, wafer thickness, and certain types of etch patterns are critical factors in controlling bonding success. Bonding experiments, in which specific flatness deviations and etch patterns have been introduced on wafers prior to bonding, have been carried out and compared to the modeling results. The understanding of the process gained through the modeling can be used to set tolerances on wafers, assist in mask layout, and guide the design of bonding equipment to ensure success in direct wafer bonding processes.

Advanced Packaging for Automotive Dashboard Application

2018 ◽  
Vol 2018 (1) ◽  
pp. 000452-000457
Author(s):  
Nokibul Islam ◽  
HC Choi
Keyword(s):  
Integrated Circuit ◽  
High Performance ◽  
Flip Chip ◽  
Wafer Level ◽  
Automotive Market ◽  
Performance Requirements ◽  
Advanced Packaging ◽  
Packaging Industry ◽  
The Right ◽  
Board Level

Abstract The current automotive market for the integrated circuit (IC) packaging industry has grown significantly due to the increasing need for automation and higher performance in vehicles. These changes in the automotive market will enable cars to be more reliable and intelligent. To address the increasingly complex demands of the automotive market, the semiconductor packaging industry is shifting its focus to prioritize the development of advanced packages for next generation automotive market requirements. Automotive IC's are traditionally wirebond packages. Due to the increasing complexity and higher performance requirements of automotive applications, the packaging industry is moving towards high performance flip chip packages for automotive infotainment, GPS, and radar applications. In this study, a comprehensive view of the evolving packaging landscape from traditional wirebond to flip chip interconnect to advanced fan-out wafer level packages will be discussed. The pros and cons of each packaging technology will be examined. Packaging roadmap details will be discussed along with assembly process information, determining the right bill of materials (BOM), and extensive package and board level reliability (BLR) including grade 1 and grade 0 reliability data will be discussed.

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