scholarly journals Selective area growth of InxGa1-xAs nanowires on HfO2 templates for highly scaled nMOS devices

MRS Advances ◽  
2019 ◽  
Vol 4 (5-6) ◽  
pp. 337-342
Author(s):  
Paloma Tejedor ◽  
Marcos Benedicto
Keyword(s):  
Field Effect Transistors ◽  
Strain Relaxation ◽  
Three Dimensional ◽  
High Mobility ◽  
Selective Growth ◽  
Oxide Semiconductor ◽  
Process Window ◽  
High Electron ◽  
Strained Si ◽  
Molecular Beam Epitaxial

ABSTRACTThe replacement of the strained Si channel in metal-oxide-semiconductor-field-effect-transistors (MOSFETs) with high electron mobility III-V compound semiconductors, particularly InGaAs, is being intensively investigated as an alternative to improve the drive current at low supply voltages in sub-10 nm CMOS applications. As device scaling continues, the reduction of the source and drain contact resistance becomes one of the most difficult challenges to fabricate highly scaled III-V-MOSFETs. In this article, we describe a self-aligned process based on selective molecular beam epitaxial regrowth of InxGa1-xAs (x=0-1) raised source/drain nanowire structures on etched recessed areas of a nanopatterned HfO2 template as a key element to integrate high mobility III-V materials with high-κ dielectrics in three-dimensional device architectures. The interaction of atomic H with the surface of the HfO2 nanopatterns has been investigated by using AFM, ToF-SIMS, and ARXPS. Selective growth has been observed for all values of x between 0 and 1. AFM results show that atomic H lowers the temperature process window for InxGa1-xAs selective growth. HRTEM images have revealed the conformality of the growth and the absence of nanotrench formation near the HfO2 mask edges. InxGa1-xAs alloys grown on H-treated HfO2 patterned substrates exhibit a higher uniformity in chemical composition and full strain relaxation for x≥0.5.

Strained Si, SiGe, and Ge channels for high-mobility metal-oxide-semiconductor field-effect transistors

2005 ◽  
Vol 97 (1) ◽  
pp. 011101 ◽  
Author(s):  
Minjoo L. Lee ◽  
Eugene A. Fitzgerald ◽  
Mayank T. Bulsara ◽  
Matthew T. Currie ◽  
Anthony Lochtefeld
Keyword(s):  
Metal Oxide ◽  
Field Effect ◽  
Field Effect Transistors ◽  
High Mobility ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Strained Si

Channel Engineering of SiGe-Based Heterostructures for High Mobility MOSFETs

2001 ◽  
Vol 686 ◽  
Author(s):  
Christopher W. Leitz ◽  
Matthew T. Currie ◽  
Minjoo L. Lee ◽  
Zhi-Yuan Cheng ◽  
Dimitri. A. Antoniadis ◽  
...  
Keyword(s):  
Field Effect Transistors ◽  
High Mobility ◽  
Hole Mobility ◽  
Oxide Semiconductor ◽  
Strained Si ◽  
Alloy Scattering ◽  
Dual Channel ◽  
Significant Performance ◽  
Performance Gains ◽  
Long Channel

AbstractStrained Si- and SiGe-based heterostructure metal-oxide-semiconductor field-effect transistors (MOSFETs) grown on relaxed SiGe virtual substrates exhibit dramatic electron and hole mobility enhancements over bulk Si, making them promising candidates for next generation complementary MOSFET (CMOS) devices. The most heavily investigated heterostructures consist of single strained Si layers grown upon relaxed SiGe substrates. While this configuration offers significant performance gains for both n- and p-MOSFETs, the enhanced hole mobility remains much lower than the enhanced electron mobility. By contrast, a combination of buried compressively strained Si1−yGey layers and tensile strained Si surface layers grown on relaxed Si1−xGex (x < y), hereafter referred to as dual channel heterostructures, offers nearly symmetric electron and hole mobilities without compromising n-MOSFET device performance. To investigate these heterostructures, we study the effects of alloy scattering on channel mobility in long channel MOSFETs. By using the combination of a buried Si0.2Ge0.8 channel and a strained Si surface channel grown on a relaxed Si0.5Ge0.5 virtual substrate, we have achieved nearly symmetric electron and hole mobility in the same heterostructure. By employing different virtual substrate compositions, we can decouple the effects of strain and alloy scattering in both tensile strained surface channels and compressively strained buried channels. We show that significant hole mobility enhancements can be achieved in dual channel heterostructures, even for buried channel compositions where alloy scattering is expected to be most severe. Furthermore, we show that alloy scattering in tensile strained SiGe surface channels impacts electrons much more severely than holes. Taken together, these results demonstrate that dual channel heterostructures can offer symmetric carrier mobilities and provide excellent performance gains for CMOS applications.

High-Electron-Mobility Ge n-Channel Metal–Oxide–Semiconductor Field-Effect Transistors with High-Pressure Oxidized Y2O3

2011 ◽  
Vol 4 (6) ◽  
pp. 064201 ◽  
Author(s):  
Tomonori Nishimura ◽  
Choong Hyun Lee ◽  
Toshiyuki Tabata ◽  
Sheng Kai Wang ◽  
Kosuke Nagashio ◽  
...  
Keyword(s):  
High Pressure ◽  
Metal Oxide ◽  
Electron Mobility ◽  
Field Effect ◽  
Field Effect Transistors ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
High Electron ◽  
High Electron Mobility

LOW TEMPERATURE MODELS OF METAL OXIDE SEMICONDUCTOR FIELD-EFFECT TRANSISTORS

1995 ◽  
Vol 06 (02) ◽  
pp. 317-373 ◽  
Author(s):  
G. GILDENBLAT ◽  
D. FOTY
Keyword(s):  
Low Temperature ◽  
Field Effect Transistors ◽  
Numerical Models ◽  
Three Dimensional ◽  
Oxide Semiconductor ◽  
Characteristic Time Scale ◽  
Mos Transistors ◽  
Short Channel ◽  
Temperature Range ◽  
Dimensional Models

We review the modeling of silicon MOS devices in the 10–300 K temperature range with an emphasis on the specifics of low-temperature operation. Recently developed one-dimensional models of long-channel transistors are discussed in connection with experimental determination and verification of the effective channel mobility in a wide temperature range. We also present analytical pseudo-two-dimensional models of short-channel devices which have been proposed for potential use in circuit simulators. Several one-, two-, and three-dimensional numerical models are discussed in order to gain insight into the more subtle details of the low-temperature device physics of MOS transistors and capacitors. Particular attention is paid to freezeout effects which, depending on the device design and the ambient temperature range, may or may not be important for actual device operation. The numerical models are applied to study the characteristic time scale of freezeout transients in the space-charge regions of silicon devices, to the analysis and suppression of delayed turn-off in MOS transistors with compensated channel, and to the temperature dependence of three-dimensional effects in short-channel, narrow-channel MOSFETs.

scholarly journals Three-Dimensional Nanoscale Mapping of State-of-the-Art Field-Effect Transistors (FinFETs)

2017 ◽  
Vol 23 (5) ◽  
pp. 916-925
Author(s):  
Pritesh Parikh ◽  
Corey Senowitz ◽  
Don Lyons ◽  
Isabelle Martin ◽  
Ty J. Prosa ◽  
...  
Keyword(s):  
Field Effect ◽  
Focused Ion Beam ◽  
Field Effect Transistors ◽  
Ion Beam ◽  
Semiconductor Industry ◽  
Three Dimensional ◽  
Atom Probe ◽  
Physical Structure ◽  
Oxide Semiconductor ◽  
Device Performance

AbstractThe semiconductor industry has seen tremendous progress over the last few decades with continuous reduction in transistor size to improve device performance. Miniaturization of devices has led to changes in the dopants and dielectric layers incorporated. As the gradual shift from two-dimensional metal-oxide semiconductor field-effect transistor to three-dimensional (3D) field-effect transistors (finFETs) occurred, it has become imperative to understand compositional variability with nanoscale spatial resolution. Compositional changes can affect device performance primarily through fluctuations in threshold voltage and channel current density. Traditional techniques such as scanning electron microscope and focused ion beam no longer provide the required resolution to probe the physical structure and chemical composition of individual fins. Hence advanced multimodal characterization approaches are required to better understand electronic devices. Herein, we report the study of 14 nm commercial finFETs using atom probe tomography (APT) and scanning transmission electron microscopy–energy-dispersive X-ray spectroscopy (STEM-EDS). Complimentary compositional maps were obtained using both techniques with analysis of the gate dielectrics and silicon fin. APT additionally provided 3D information and allowed analysis of the distribution of low atomic number dopant elements (e.g., boron), which are elusive when using STEM-EDS.

scholarly journals Growth of high-quality semiconducting tellurium films for high-performance p-channel field-effect transistors with wafer-scale uniformity

2022 ◽  
Vol 6 (1) ◽  
Author(s):  
Taikyu Kim ◽  
Cheol Hee Choi ◽  
Pilgyu Byeon ◽  
Miso Lee ◽  
Aeran Song ◽  
...  
Keyword(s):  
Field Effect ◽  
Physical Vapor Deposition ◽  
High Performance ◽  
Supply Voltage ◽  
Field Effect Transistors ◽  
Low Cost ◽  
Three Dimensional ◽  
Cmos Technology ◽  
Oxide Semiconductor ◽  
Wafer Scale

AbstractAchieving high-performance p-type semiconductors has been considered one of the most challenging tasks for three-dimensional vertically integrated nanoelectronics. Although many candidates have been presented to date, the facile and scalable realization of high-mobility p-channel field-effect transistors (FETs) is still elusive. Here, we report a high-performance p-channel tellurium (Te) FET fabricated through physical vapor deposition at room temperature. A growth route involving Te deposition by sputtering, oxidation and subsequent reduction to an elemental Te film through alumina encapsulation allows the resulting p-channel FET to exhibit a high field-effect mobility of 30.9 cm2 V−1 s−1 and an ION/OFF ratio of 5.8 × 105 with 4-inch wafer-scale integrity on a SiO2/Si substrate. Complementary metal-oxide semiconductor (CMOS) inverters using In-Ga-Zn-O and 4-nm-thick Te channels show a remarkably high gain of ~75.2 and great noise margins at small supply voltage of 3 V. We believe that this low-cost and high-performance Te layer can pave the way for future CMOS technology enabling monolithic three-dimensional integration.

The Effect of Strain on the Formation of Dislocations at the SiGe/Si Interface

MRS Bulletin ◽  
1996 ◽  
Vol 21 (4) ◽  
pp. 38-44 ◽  
Author(s):  
F.K. LeGoues
Keyword(s):  
Metal Oxide ◽  
High Speed ◽  
High Performance ◽  
Field Effect Transistors ◽  
Low Cost ◽  
Complementary Metal Oxide Semiconductor ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Design Rule ◽  
Strained Si

Recently much interest has been devoted to Si-based heteroepitaxy, and in particular, to the SiGe/Si system. This is mostly for economical reasons: Si-based technology is much more advanced, is widely available, and is cheaper than GaAs-based technology. SiGe opens the door to the exciting (and lucrative) area of Si-based high-performance devices, although optical applications are still limited to GaAs-based technology. Strained SiGe layers form the base of heterojunction bipolar transistors (HBTs), which are currently used in commercial high-speed analogue applications. They promise to be low-cost compared to their GaAs counterparts and give comparable performance in the 2-20-GHz regime. More recently we have started to investigate the use of relaxed SiGe layers, which opens the door to a wider range of application and to the use of SiGe in complementary metal oxide semiconductor (CMOS) devices, which comprise strained Si and SiGe layers. Some recent successes include record-breaking low-temperature electron mobility in modulation-doped layers where the mobility was found to be up to 50 times better than standard Si-based metal-oxide-semiconductor field-effect transistors (MOSFETs). Even more recently, SiGe-basedp-type MOSFETS were built with oscillation frequency of up to 50 GHz, which is a new record, in anyp-type material for the same design rule.

Bandstructure Near Misfit Dislocations in Si Quantum Wells

1998 ◽  
Vol 4 (S2) ◽  
pp. 794-795
Author(s):  
P.E. Batson
Keyword(s):  
Quantum Wells ◽  
Conduction Band ◽  
Electron Mobility ◽  
Axial Strain ◽  
Strain Relaxation ◽  
Local Potential ◽  
Misfit Dislocations ◽  
High Electron ◽  
Strained Si ◽  
Growth Interface

High electron mobility structures have been built for several years now using strained silicon layers grown on SixGe(1-x) with x in the 25-40% range. In these structures, a thin layer of silicon is grown between layers of unstrained GeSi alloy. Matching of the two lattices in the plane of growth produces a bi-axial strain in the silicon, splitting the conduction band and providing light electron levels for enhanced mobility. If the silicon channel becomes too thick, strain relaxation can occur by injection of misfit dislocations at the growth interface between the silicon and GeSi alloy. The strain field of these dislocations then gives rise to a local potential variation that limits electron mobility in the strained Si channel. This study seeks to verify this mechanism by measuring the absolute conduction band shifts which track the local potential near the misfit dislocations.

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