Effects of Surface Doping of Si Absorbers on the Band Alignment and Electrical Performance of TiO2-Based Electron-Selective Contacts

MRS Advances ◽  
2019 ◽  
Vol 4 (13) ◽  
pp. 769-775 ◽  
Author(s):  
Hyunju Lee ◽  
Takefumi Kamioka ◽  
Noritaka Usami ◽  
Yoshio Ohshita
Keyword(s):  
Electrical Transport ◽  
Energy Levels ◽  
Band Alignment ◽  
Electrical Performance ◽  
Si Substrate ◽  
Si Substrates ◽  
Conduction Band Offset ◽  
Electron Transport Property ◽  
Xps Study ◽  
Phosphorus Doped

ABSTRACTWe have investigated the chemical and electrical properties of a thin SiO2/TiO2 stacking layer deposited on n-Si and heavily phosphorus-doped n++ Si substrates to elucidate effects of phosphorus doping of Si absorbers on the band alignment and electrical performance of a SiO2/TiO2 stack-based electron-selective contact deposited on the differently doped Si substrates. From our XPS study, we show a shift of the TiO2 energy levels up to ∼0.13 eV with respect to those of Si as the doping level of Si substrates changes. We also show that the conduction band offset of the SiO2/TiO2 stacking layer at the interface with the n++ Si substrate seems to smaller than that of the SiO2/TiO2 stacking layer at the interface with n-Si substrate. Finally, from our electrical transport measurements, we could conclude that the thinner tunneling barrier, the increased electron density in front of the SiO2 layer in the n++ Si surface, and/or the reduced barrier height by heavy doping, seem to enhance the majority electron transport property of the SiO2/TiO2/n++ Si samples compared to that of the SiO2/TiO2/n-Si samples.

scholarly journals Surface Texturing of Si with Periodically Arrayed Oblique Nanopillars to Achieve Antireflection

Materials ◽  
2021 ◽  
Vol 14 (2) ◽  
pp. 380
Author(s):  
Jun-Hyun Kim ◽  
Sanghyun You ◽  
Chang-Koo Kim
Keyword(s):  
Aspect Ratio ◽  
Plasma Etching ◽  
Surface Texturing ◽  
Light Reflection ◽  
Si Substrate ◽  
Weighted Mean ◽  
Optical Reflectance ◽  
Si Substrates ◽  
Aspect Ratios ◽  
Shadowing Effect

Si surfaces were texturized with periodically arrayed oblique nanopillars using slanted plasma etching, and their optical reflectance was measured. The weighted mean reflectance (Rw) of the nanopillar-arrayed Si substrate decreased monotonically with increasing angles of the nanopillars. This may have resulted from the increase in the aspect ratio of the trenches between the nanopillars at oblique angles due to the shadowing effect. When the aspect ratios of the trenches between the nanopillars at 0° (vertical) and 40° (oblique) were equal, the Rw of the Si substrates arrayed with nanopillars at 40° was lower than that at 0°. This study suggests that surface texturing of Si with oblique nanopillars reduces light reflection compared to using a conventional array of vertical nanopillars.

scholarly journals Formation and Evaluation of Silicon Substrate with Highly-Doped Porous Si Layers Formed by Metal-Assisted Chemical Etching

2021 ◽  
Vol 16 (1) ◽  
Author(s):  
Yijie Li ◽  
Nguyen Van Toan ◽  
Zhuqing Wang ◽  
Khairul Fadzli Bin Samat ◽  
Takahito Ono
Keyword(s):  
Electrical Conductivity ◽  
Seebeck Coefficient ◽  
Contact Resistance ◽  
Power Factor ◽  
Chemical Etching ◽  
Porous Si ◽  
Si Substrate ◽  
Si Substrates ◽  
Output Performance ◽  
Metal Assisted Chemical Etching

AbstractPorous silicon (Si) is a low thermal conductivity material, which has high potential for thermoelectric devices. However, low output performance of porous Si hinders the development of thermoelectric performance due to low electrical conductivity. The large contact resistance from nonlinear contact between porous Si and metal is one reason for the reduction of electrical conductivity. In this paper, p- and n-type porous Si were formed on Si substrate by metal-assisted chemical etching. To decrease contact resistance, p- and n-type spin on dopants are employed to dope an impurity element into p- and n-type porous Si surface, respectively. Compared to the Si substrate with undoped porous samples, ohmic contact can be obtained, and the electrical conductivity of doped p- and n-type porous Si can be improved to 1160 and 1390 S/m, respectively. Compared with the Si substrate, the special contact resistances for the doped p- and n-type porous Si layer decreases to 1.35 and 1.16 mΩ/cm2, respectively, by increasing the carrier concentration. However, the increase of the carrier concentration induces the decline of the Seebeck coefficient for p- and n-type Si substrates with doped porous Si samples to 491 and 480 μV/K, respectively. Power factor is related to the Seebeck coefficient and electrical conductivity of thermoelectric material, which is one vital factor that evaluates its output performance. Therefore, even though the Seebeck coefficient values of Si substrates with doped porous Si samples decrease, the doped porous Si layer can improve the power factor compared to undoped samples due to the enhancement of electrical conductivity, which facilitates its development for thermoelectric application.

Heteroepitaxial Growth of 3C-SiC on Si (111) Substrate Using AlN as a Buffer Layer

2008 ◽  
Vol 600-603 ◽  
pp. 251-254 ◽  
Author(s):  
Yong Mei Zhao ◽  
Guo Sheng Sun ◽  
Xing Fang Liu ◽  
Jia Ye Li ◽  
Wan Shun Zhao ◽  
...  
Keyword(s):  
Buffer Layer ◽  
Chemical Vapor ◽  
Heteroepitaxial Growth ◽  
Si Substrate ◽  
Si Substrates ◽  
Good Crystallinity ◽  
Aln Film ◽  
Pressure Chemical ◽  
Aln Buffer ◽  
Sic Film

Using AlN as a buffer layer, 3C-SiC film has been grown on Si substrate by low pressure chemical vapor deposition (LPCVD). Firstly growth of AlN thin films on Si substrates under varied V/III ratios at 1100oC was investigated and the (002) preferred orientational growth with good crystallinity was obtained at the V/III ratio of 10000. Annealing at 1300oC indicated the surface morphology and crystallinity stability of AlN film. Secondly the 3C-SiC film was grown on Si substrate with AlN buffer layer. Compared to that without AlN buffer layer, the crystal quality of the 3C-SiC film was improved on the AlN/Si substrate, characterized by X-ray diffraction (XRD) and Raman measurements.

XPS study on band alignment at PtO-terminated ZnO(0001) interface

2010 ◽  
Vol 42 (10-11) ◽  
pp. 1528-1531 ◽  
Author(s):  
Taeyoung Kim ◽  
Michiko Yoshitake ◽  
Shinjiro Yagyu ◽  
Slavomir Nemsak ◽  
Takahiro Nagata ◽  
...  
Keyword(s):  
Band Alignment ◽  
Xps Study

Effect of heating on electrical transport in AlGaN/GaN Schottky barrier diodes on Si substrate

2014 ◽  
Vol 14 ◽  
pp. S98-S102 ◽  
Author(s):  
Hyeonseok Woo ◽  
Yongcheol Jo ◽  
Jongmin Kim ◽  
Cheonghyun Roh ◽  
Junho Lee ◽  
...  
Keyword(s):  
Schottky Barrier ◽  
Electrical Transport ◽  
Schottky Barrier Diodes ◽  
Si Substrate

scholarly journals Magnetic Characteristics of Mn-Implanted GaN Nanorods Followed by Thermal Annealing

2012 ◽  
Vol 2012 ◽  
pp. 1-6
Author(s):  
Im Taek Yoon ◽  
Yoon Shon ◽  
Younghae Kwon ◽  
Young S. Park ◽  
Chang Soo Park ◽  
...  
Keyword(s):  
Molecular Beam ◽  
Magnetic Phase ◽  
Structural Disorder ◽  
Magnetic Characteristics ◽  
Radio Frequency Plasma ◽  
Si Substrate ◽  
Ferromagnetic Property ◽  
Si Substrates ◽  
Annealing Step ◽  
Frequency Plasma

We have investigated the magnetic and optical properties of dislocation-free vertical GaN nanorods with diameters of 150 nm grown on (111) Si substrates by radio-frequency plasma-assisted molecular-beam epitaxy followed by Mn ion implantation and annealing. The GaN nanorods are fully relaxed and have a very good crystal quality characterized by extremely strong and narrow photoluminescence excitonic lines near 3.47 eV. For GaMnN nanorods, it can be concluded that the ferromagnetic property of GaMnN nanorod with a Curie temperature over 300 K is associated with the formation of Mn4Si7magnetic phase which results from the effects of magnetic and structural disorder introduced by a random incorporation and inhomogeneous distribution of Mn atoms in the porous layer between the nanorods that form precipitates in the Si substrate before or during the annealing step amongst the GaN nanorods.

Retarded Growth of Sputtered HfO2 Films on Germanium

2004 ◽  
Vol 811 ◽  
Author(s):  
Koji Kita ◽  
Masashi Sasagawa ◽  
Masahiro Toyama ◽  
Kentaro Kyuno ◽  
Akira Toriumi
Keyword(s):  
Film Growth ◽  
Early Stage ◽  
Gate Oxide ◽  
Interface Layer ◽  
Film Deposition ◽  
Si Substrate ◽  
Equivalent Thickness ◽  
Ternary Compounds ◽  
Si Substrates

ABSTRACTHfO2 films were deposited by reactive sputtering on Ge and Si substrates simultaneously, and we found not only the interface layer but the HfO2 film was thinner on Ge substrate compared with that on Si substrate. A metallic Hf layer has a crucial role for the thickness differences of both interface layer and HfO2 film, since those thickness differences were observed only when an ultrathin metallic Hf layer was predeposited before HfO2 film deposition. The role of metallic Hf is understandable by assuming a formation of volatile Hf-Ge-O ternary compounds at the early stage of film growth. These results show an advantage of HfO2/Ge over HfO2/Si systems from the viewpoint of further scaling of electrical equivalent thickness of the gate oxide films.

Semi-Insulating Silicon for Microwave Devices

2009 ◽  
Vol 156-158 ◽  
pp. 101-106 ◽  
Author(s):  
Douglas M. Jordan ◽  
Kanad Mallik ◽  
Robert J. Falster ◽  
Peter R. Wilshaw
Keyword(s):  
Room Temperature ◽  
Energy Levels ◽  
Silicon On Insulator ◽  
Microwave Devices ◽  
Insulating Material ◽  
Czochralski Silicon ◽  
Boron Doped ◽  
Microwave Applications ◽  
Soi Substrates ◽  
Phosphorus Doped

The concept of fully encapsulated, semi-insulating silicon (SI-Si), Czochralski-silicon-on-insulator (CZ-SOI) substrates for silicon microwave devices is presented. Experimental results show that, using gold as a compensating impurity, a Si resistivity of order 400 kΩcm can be achieved at room temperature using lightly phosphorus doped substrates. This compares favourably with the maximum of ~180kΩcm previously achieved using lightly boron doped wafers and is due to a small asymmetry of the position of the two gold energy levels introduced into the band gap. Measurements of the temperature dependence of the resistivity of the semi-insulating material show that a resistivity ~5kΩcm can be achieved at 100°C. Thus the substrates are suitable for microwave devices working at normal operating temperatures and should allow Si to be used for much higher frequency microwave applications than currently possible.

scholarly journals Characterization of Gaas/Si/GaAs Heterointerfaces

1989 ◽  
Vol 148 ◽  
Author(s):  
Zuzanna Liliental-Weber ◽  
Raymond P. Mariella
Keyword(s):  
Electron Microscopy ◽  
Transmission Electron Microscopy ◽  
Low Temperature ◽  
Defect Density ◽  
Si Substrate ◽  
Reverse Polarity ◽  
Si Substrates ◽  
Transmission Electron ◽  
Metal Semiconductor Metal

ABSTRACTTransmission electron microscopy of GaAs grown on Si for metal-semiconductor-metal photodetectors is presented in this paper. Two kinds of samples are compared: GaAs grown on a 15 Å Si epilayer grown on GaAs, and GaAs grown at low temperature (300°C) on Si substrates. It is shown that the GaAs epitaxial layer grown on thin Si layer has reverse polarity to the substrate (antiphase relation). Higher defect density is observed for GaAs grown on Si substrate. This higher defect density correlates with an increased device speed, but with reduced sensitivity.

Influence of Interface States on Output Characteristics of 4H-SiC MESFETs on Semi–Insulating Substrates

2000 ◽  
Vol 640 ◽  
Author(s):  
Nabil Sghaier ◽  
Abdel K. Souifi ◽  
Jean-Marie Bluet ◽  
Manuel Berenguer ◽  
Gérard Guillot ◽  
...  
Keyword(s):  
Gate Voltage ◽  
Frequency Dispersion ◽  
Buffer Layers ◽  
Si Substrate ◽  
Substrate Interface ◽  
Si Substrates ◽  
Kink Effect ◽  
Parasitic Effect ◽  
Output Characteristics ◽  
Output Conductance

ABSTRACTThe aim of this work is to study the origin of parasitic phenomena in the output characteristics of 4H-SiC MESFETs on semi-insulating (SI) substrates with various buffer layers. Ids-Vds measurements as a function of temperature have first been performed. Different parasitic effects such as kink effect, hysteresis effect when the gate voltage is successively increased or decreased, or changes in the output characteristics after a high drain polarization are presented. Random Telegraph Signal (RTS) measurements and frequency dispersion of the output conductance have next been realized. From the obtained results, we propose that the parasitic effect on the output characteristics are correlated with the presence of deep levels located near the semi -insulating substrate interface. The main observed trap is tentatively attributed to the presence of Vanadium in the SI substrate.

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