Performance comparison of flux schemes for numerical simulation of high-speed inviscid flows

2014 ◽  
Vol 14 (2) ◽  
pp. 83 ◽  
Author(s):  
Bibin John ◽  
G. Sarath ◽  
Vinayak Kulkarni ◽  
Ganesh Natarajan
Keyword(s):  
Numerical Simulation ◽  
High Speed ◽  
Performance Comparison ◽  
Inviscid Flows

Numerical simulation of high-speed civil transport inlet operability with angle of attack

AIAA Journal ◽  
1998 ◽  
Vol 36 ◽  
pp. 1223-1229
Author(s):  
Ge-Cheng Zha ◽  
Doyle Knight ◽  
Donald Smith ◽  
Martin Haas
Keyword(s):  
Numerical Simulation ◽  
High Speed ◽  
Angle Of Attack

Numerical Simulation of High-Speed Crack Propagating and Branching Phenomena

2016 ◽  
Vol 37 (7) ◽  
pp. 729-739
Author(s):  
GU Xin-bao ◽  
◽  
ZHOU Xiao-ping ◽  
XU Xiao ◽  
Keyword(s):  
Numerical Simulation ◽  
High Speed

scholarly journals Systematic Performance Comparison of (Duobinary)-PAM-2,4 Signaling under Light and Strong Opto-Electronic Bandwidth Conditions

Photonics ◽  
2021 ◽  
Vol 8 (3) ◽  
pp. 81
Author(s):  
Ramón Gutiérrez-Castrejón ◽  
Md Ghulam Saber ◽  
Md Samiul Alam ◽  
Zhenping Xing ◽  
Eslam El-Fiky ◽  
...  
Keyword(s):  
Optical Networks ◽  
High Speed ◽  
Performance Comparison ◽  
Sampling Point ◽  
Bit Rate ◽  
Performance Limits ◽  
Specific System ◽  
Rate System ◽  
Modulation Formats ◽  
Modulation Format

We present a systematic comparison of PAM-2 (NRZ), Duobinary-PAM-2, PAM-4, and Duobinary-PAM-4 (duo-quaternary) signaling in the context of short-reach photonic communications systems using a Mach–Zehnder modulator as transmitter. The effect on system performance with a relaxed and constrained system’s opto-electronic bandwidth is analyzed for bit rates ranging from 20 to 116 Gb/s. In contrast to previous analyses, our approach employs the same experimental and simulation conditions for all modulation formats. Consequently, we were able to confidently determine the performance limits of each format for particular values of bit rate, system bandwidth, transmitter chirp, and fiber dispersion. We demonstrate that Duobinary-PAM-4 is a good signaling choice only for bandwidth-limited systems operating at relatively high speed. Otherwise, PAM-4 represents a more sensible choice. Moreover, our analysis put forward the existence of transition points: specific bit rate values where the BER versus bit rate curves for two different formats cross each other. They indicate the bit rate values where, for specific system conditions, switching from one modulation to another guarantees optimum performance. Their existence naturally led to the proposal of a format-selective transceiver, a component that, according to network conditions, operates with the most adequate modulation format. Since all analyzed modulations share similar implementation details, signaling switching is achieved by simply changing the sampling point and threshold count at the receiver, bringing flexibility to IM/DD-based optical networks.

Numerical Simulation of Flowfield around High Speed Trains Passing by each other at the same Speed

2011 ◽  
Vol 97-98 ◽  
pp. 698-701
Author(s):  
Ming Lu Zhang ◽  
Yi Ren Yang ◽  
Li Lu ◽  
Chen Guang Fan
Keyword(s):  
Numerical Simulation ◽  
Wind Tunnel ◽  
Flow Field ◽  
Point Source ◽  
High Speed ◽  
Stokes Equations ◽  
Field Structure ◽  
Vehicle Speed ◽  
Mesh Method ◽  
High Speed Trains

Large eddy simulation (LES) was made to solve the flow around two simplified CRH2 high speed trains passing by each other at the same speed base on the finite volume method and dynamic layering mesh method and three dimensional incompressible Navier-Stokes equations. Wind tunnel experimental method of resting train with relative flowing air and dynamic mesh method of moving train were compared. The results of numerical simulation show that the flow field structure around train is completely different between wind tunnel experiment and factual running. Two opposite moving couple of point source and point sink constitute the whole flow field structure during the high speed trains passing by each other. All of streamlines originate from point source (nose) and finish with the closer point sink (tail). The flow field structure around train is similar with different vehicle speed.

A Characteristic-Featured Shock Wave Indicator for Simulating High-Speed Inviscid Flows on 3D Unstructured Mesh

2021 ◽  
Author(s):  
Yiwei Feng ◽  
Tiegang Liu ◽  
Xiaofeng He ◽  
Bin Zhang ◽  
Kun Wang
Keyword(s):  
Shock Wave ◽  
High Speed ◽  
Unstructured Mesh ◽  
High Efficiency ◽  
Flow Simulation ◽  
Attractive Alternative ◽  
Inviscid Flows ◽  
Speed Flow ◽  
Flow Compression ◽  
Shock Processing

Abstract In this work, we extend the characteristic-featured shock wave indicator based on artificial neuron training to 3D high-speed flow simulation on unstructured mesh. The extension is achieved through dimension splitting. This leads to that the proposed indicator is capable of identifying regions of flow compression in any direction. With this capability, the indicator is further developed to combine with h-adaptivity of mesh refinement to improve resolution with less computational costs. The present indicator provided an attractive alternative for constructing high-resolution, high-efficiency shock-processing method to simulate high-speed inviscid flows.

scholarly journals Performance Comparison of Carry-Lookahead and Carry-Select Adders Based on Accurate and Approximate Additions

Electronics ◽  
2018 ◽  
Vol 7 (12) ◽  
pp. 369 ◽  
Author(s):  
Padmanabhan Balasubramanian ◽  
Nikos Mastorakis
Keyword(s):  
High Speed ◽  
Digital Signal ◽  
Complementary Metal Oxide Semiconductor ◽  
Performance Comparison ◽  
Oxide Semiconductor ◽  
Cmos Process ◽  
Least Significant Bit ◽  
Design Metrics ◽  
Ripple Carry Adder ◽  
Speed Performance

Addition is a fundamental operation in microprocessing and digital signal processing hardware, which is physically realized using an adder. The carry-lookahead adder (CLA) and the carry-select adder (CSLA) are two popular high-speed, low-power adder architectures. The speed performance of a CLA architecture can be improved by adopting a hybrid CLA architecture which employs a small-size ripple-carry adder (RCA) to replace a sub-CLA in the least significant bit positions. On the other hand, the power dissipation of a CSLA employing full adders and 2:1 multiplexers can be reduced by utilizing binary-to-excess-1 code (BEC) converters. In the literature, the designs of many CLAs and CSLAs were described separately. It would be useful to have a direct comparison of their performances based on the design metrics. Hence, we implemented homogeneous and hybrid CLAs, and CSLAs with and without the BEC converters by considering 32-bit accurate and approximate additions to facilitate a comparison. For the gate-level implementations, we considered a 32/28 nm complementary metal-oxide-semiconductor (CMOS) process targeting a typical-case process–voltage–temperature (PVT) specification. The results show that the hybrid CLA/RCA architecture is preferable among the CLA and CSLA architectures from the speed and power perspectives to perform accurate and approximate additions.

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