Efficient implementation of power analysis attack resistant advanced encryption standard algorithm on side-channel attack standard evaluation board

2016 ◽  
Vol 6 (3) ◽  
pp. 203
Author(s):  
Massoud Masoumi ◽  
Pouya Habibi ◽  
Ali Dehghan ◽  
Mohammad Jadidi ◽  
Leila Yousefi
Keyword(s):  
Power Analysis ◽  
Efficient Implementation ◽  
Advanced Encryption Standard ◽  
Side Channel ◽  
Side Channel Attack ◽  
Standard Algorithm ◽  
Evaluation Board ◽  
Power Analysis Attack

scholarly journals A Novel AES Cryptographic Core Highly Resistant to Differential Power Analysis Attacks

2009 ◽  
Vol 4 (1) ◽  
pp. 29-35
Author(s):  
Felipe Ghellar ◽  
Marcelo Lubaszewski
Keyword(s):  
Power Analysis ◽  
Design Space Exploration ◽  
Design Space ◽  
Space Exploration ◽  
Building Blocks ◽  
Advanced Encryption Standard ◽  
Side Channel ◽  
Performance Constraints ◽  
Mathematical Properties ◽  
Rijndael Algorithm

In this work, we present a novel core implementation of the Advanced Encryption Standard with an integrated countermeasure against side channel attacks, which can theoretically increase the complexity of a DPA attack by a factor of 240. This countermeasure is based on mathematical properties of the Rijndael algorithm, and retains compatibility with the published Standard. The entire system was designed from the ground up to allow the reutilization of the building blocks in many different combinations, thus providing for design space exploration. Synthesis results show that the protected core can perfectly meet the performance constraints of currently used smart cards.

scholarly journals An Efficient Correlation Power Analysis Attack Using Variational Mode Decomposition 

2020 ◽  
Vol 31 (1) ◽  
pp. 17-25
Keyword(s):  
Power Analysis ◽  
Side Channel ◽  
Variational Mode Decomposition ◽  
Secret Key ◽  
Intrinsic Mode Functions ◽  
Side Channel Attacks ◽  
Mode Decomposition ◽  
Noisy Conditions ◽  
Correlation Power Analysis ◽  
Evaluation Board

Side channel attacks (SCAs) are now a real threat to cryptographic devices and correlation power analysis (CPA) is the most powerful attack. So far, a CPA attack usually exploits the leakage information from raw power consumption traces that collected from the attack device. In real attack scenarios, these traces collected from measurement equipment are usually contaminated by noise resulting in a decrease in attack efficiency. In this paper, we propose a variant CPA attack that exploits the leakage information from intrinsic mode functions (IMFs) of the power traces. These IMFs are the results of the variational mode decomposition (VMD) process on the raw power traces. This attack technique decreases the number of power traces for correctly recovering the secret key by approximately 13% in normal conditions and 60% in noisy conditions compared to a traditional CPA attack. Experiments were performed on power traces of AES-128 implemented in both microcontroller and FPGA by Sakura-G/W side channel evaluation board to verify the effectiveness of our method.

scholarly journals Charge Based Power Side-Channel Attack Methodology for an Adiabatic Cipher

Electronics ◽  
2021 ◽  
Vol 10 (12) ◽  
pp. 1438
Author(s):  
Krithika Dhananjay ◽  
Emre Salman
Keyword(s):  
Power Analysis ◽  
Block Cipher ◽  
Side Channel ◽  
Secret Key ◽  
Side Channel Attack ◽  
Ultra Low Power ◽  
Target Signal ◽  
Adiabatic Circuit ◽  
A Charge ◽  
The Internet Of Things

SIMON is a block cipher developed to provide flexible security options for lightweight hardware applications such as the Internet-of-things (IoT). Safeguarding such resource-constrained hardware from side-channel attacks poses a significant challenge. Adiabatic circuit operation has recently received attention for such applications due to ultra-low power consumption. In this work, a charge-based methodology is developed to mount a correlation power analysis (CPA) based side-channel attack to an adiabatic SIMON core. The charge-based method significantly reduces the attack complexity by reducing the required number of power samples by two orders of magnitude. The CPA results demonstrate that the required measurements-to-disclosure (MTD) to retrieve the secret key of an adiabatic SIMON core is 4× higher compared to a conventional static CMOS based implementation. The effect of increase in the target signal load capacitance on the MTD is also investigated. It is observed that the MTD can be reduced by half if the load driven by the target signal is increased by 2× for an adiabatic SIMON, and by 5× for a static CMOS based SIMON. This sensitivity to target signal capacitance of the adiabatic SIMON can pose a serious concern by facilitating a more efficient CPA attack.

NEMR: A Nonequidistant DPA Attack-Proof of Modular Reduction in a CRT Implementation of RSA

2018 ◽  
Vol 27 (12) ◽  
pp. 1850191 ◽  
Author(s):  
S. Kaedi ◽  
M. Doostari ◽  
M. B. Ghaznavi-Ghoushchi
Keyword(s):  
Digital Signature ◽  
Power Analysis ◽  
Input Data ◽  
Side Channel ◽  
Reduction Step ◽  
Side Channel Attacks ◽  
Differential Power Analysis ◽  
Embedded Design ◽  
Power Analysis Attack

One of the most common algorithms in a digital signature is the RSA-CRT. Several side channel attacks have been presented on the RSA-CRT’s embedded design. Such attacks are divided into two categories: attack in the modular reduction step and attack in the recombination step. The former are plaintext attacks and based on the modular reduction on equidistant data attack, which is introduced in [B. den Boer, et al., “A DPA attack against the modular reduction within a CRT implementation of RSA,” in CHES 2002]. In these attacks, instead of using random plaintext, an equidistant series of input data is used. In a chosen and equidistant plaintext attack, the attacker needs a higher level of accessibility, and it is more difficult than a nonchosen plaintext attack. In this paper, we present a nonequidistant plaintext (but chosen plaintext) differential power analysis attack on the modular reduction in RSA-CRT, named NEMR (nonequidistant plaintext on modular reduction). We also present a new countermeasure on NEMR attack, which is resistant against equidistant and nonequidistant data attack on reduction step in RSA-CRT. In order to prove the idea, the NEMR attack is applied on the RSA-CRT 2048-bit implementation on SAKURA-G board, and the result is evaluated. Then, the presented countermeasure on NEMR attack is tested, and practical results demonstrate the validity of the proposed approach.

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