Design of high density one time programmable memory in standard CMOS process

2009 ◽  
Author(s):  
Kwok Ping Ng
Keyword(s):  
High Density ◽  
Cmos Process ◽  
Standard Cmos Process

Novel Chain Stack Capacitor for 32Mb FeRAM and Beyond

2002 ◽  
Vol 748 ◽  
Author(s):  
R. Bruchhaus ◽  
T. Ozaki ◽  
U. Ellerkmann ◽  
J. Lian ◽  
Y. Kumura ◽  
...  
Keyword(s):  
Bottom Electrode ◽  
Fatigue Behavior ◽  
Ferroelectric Material ◽  
Small Cell ◽  
High Density ◽  
Cmos Process ◽  
Cell Design ◽  
Ferroelectric Capacitor ◽  
Standard Cmos Process ◽  
Sputter Deposited

ABSTRACTFor high density FeRAM devices small cell sizes are essential. The combination of the capacitor on plug (COP) structure with the Chain FeRAM™ cell design is used to develop a 32Mb FeRAM. Based on a 0.2 μm standard CMOS process a silicide capped polysilicon plug is used to contact the bottom electrode of the ferroelectric capacitor to the transistor. The barrier contact to the plug is formed by IrO2/Ir and a sputter deposited PZT (40/60) is used as ferroelectric material. The function of SrRuO3 (SRO) layers at the electrode/PZT interfaces is described in more detail. Double sided SRO results in slightly lower coercive voltage and imprint behavior compared to capacitors without SRO. Double sided SRO is essential to achieve excellent fatigue behavior measured up to 1×1011 switching cycles.

Fabrication of Monolithic Integrated Bimaterial Resonant Uncooled IR Sensor

2013 ◽  
Vol 543 ◽  
pp. 176-179 ◽  
Author(s):  
D.Q. Zhao ◽  
Xia Zhang ◽  
P. Liu ◽  
F. Yang ◽  
C. Lin ◽  
...  
Keyword(s):  
Silicon Nitride ◽  
Hole Mobility ◽  
Micro Electro Mechanical System ◽  
Cmos Process ◽  
Standard Cmos Process ◽  
Ir Sensor ◽  
Cantilever Structure ◽  
Cmos Mems ◽  
On Chip ◽  
Micro Cantilever

In this work we studied the fabrication of a monolithic bimaterial micro-cantilever resonant IR sensor with on-chip drive circuits. The effects of high temperature process and stress induced performance degradation were investigated. The post-CMOS MEMS (micro electro mechanical system) fabrication process of this IR sensor is the focus of this paper, starting from theoretical analysis and simulation, and then moving to experimental verification. The capacitive cantilever structure was fabricated by surface micromachining method, and drive circuits were prepared by standard CMOS process. While the stress introduced by MEMS films, such as the tensile silicon nitride which works as a contact etch stopper layer for MOSFETs and releasing stop layer for the MEMS structure, increases the electron mobility of NMOS, PMOS hole mobility decreases. Moreover, the NMOS threshold voltage (Vth) shifts, and transconductance (Gm) degrades. An additional step of selective removing silicon nitride capping layer and polysilicon layer upon IC area were inserted into the standard CMOS process to lower the stress in MOSFET channel regions. Selective removing silicon nitride and polysilicon before annealing can void 77% Vth shift and 86% Gm loss.

scholarly journals Integration Of Surface Micromachined Polysilicon Mirrors And A Standard Cmos Process

2005 ◽  
Author(s):  
M. Fischer ◽  
M. Nagele ◽  
D. Eichner ◽  
C. Schollhorn ◽  
R. Strobel
Keyword(s):  
Cmos Process ◽  
Standard Cmos Process

scholarly journals Silicon photonic temperature sensor
employing a ring resonator manufactured
using a standard CMOS process

2010 ◽  
Vol 18 (21) ◽  
pp. 22215 ◽  
Author(s):  
Gun-Duk Kim ◽  
Hak-Soon Lee ◽  
Chang-Hyun Park ◽  
Sang-Shin Lee ◽  
Boo Tak Lim ◽  
...  
Keyword(s):  
Temperature Sensor ◽  
Ring Resonator ◽  
Cmos Process ◽  
Standard Cmos Process ◽  
Silicon Photonic

scholarly journals High Speed and High Responsivity Avalanche Photodiode Fabricated by Standard CMOS Process in Blue Wavelength Region

2018 ◽  
Vol E101.C (7) ◽  
pp. 574-580
Author(s):  
Koichi IIYAMA ◽  
Takeo MARUYAMA ◽  
Ryoichi GYOBU ◽  
Takuya HISHIKI ◽  
Toshiyuki SHIMOTORI
Keyword(s):  
High Speed ◽  
Wavelength Region ◽  
Avalanche Photodiode ◽  
Cmos Process ◽  
High Responsivity ◽  
Standard Cmos Process ◽  
Blue Wavelength

Impact of Backend Processing on Integrated Ferroelectric Capacitor Characteristics

1993 ◽  
Vol 310 ◽  
Author(s):  
P.D. Maniar ◽  
R. Moazzami ◽  
R.E. Jones ◽  
A.C. Campbell ◽  
C.J. Mogab
Keyword(s):  
Leakage Current ◽  
Sol Gel ◽  
Low Pressure ◽  
Cmos Process ◽  
Ferroelectric Capacitor ◽  
Standard Cmos Process ◽  
Order Of Magnitude ◽  
Pressure Hydrogen

AbstractIntegration of a ferroelectric capacitor module in a standard CMOS process subjects the ferroelectric to various ambients during backend processing, some of which can render the ferroelectric essentially non-operational for NVRAM applications. Post-crystallization processing of sol-gel deposited integrated ferroelectric PZT capacitors in the presence of hydrogen-containing, reducing ambients is observed to degrade the nonvolatile polarization. Low-pressure hydrogen anneals at temperatures as low as 200°C substantially degrade the nonvolatile polarization while the DRAM polarization remains roughly constant. Leakage current drops by one order of magnitude and fatigue is accelerated. A ferroelectric capacitor module can be integrated with minimal degradation with careful modifications in the backend processing.

High photon detection efficiency single photon avalanche diode in 0.18 μm standard CMOS process

2017 ◽  
Vol 31 (17) ◽  
pp. 1750193 ◽  
Author(s):  
Wei Wang ◽  
Xiaoyuan Bao ◽  
Li Chen ◽  
Ting Chen ◽  
Guanyu Wang ◽  
...  
Keyword(s):  
Breakdown Voltage ◽  
Bias Voltage ◽  
Detection Efficiency ◽  
Single Photon ◽  
Cmos Process ◽  
Guard Ring ◽  
Reverse Bias Voltage ◽  
Photon Detection ◽  
Standard Cmos Process ◽  
Photon Detection Efficiency

This paper proposed a single photon avalanche diodes (SPADs) designed with 0.18 [Formula: see text] standard CMOS process. One of the major challenges in CMOS SPADs is how to raise the low photon detection efficiency (PDE). In this paper, the device structure and process parameters of the CMOS SPAD are optimized so as to improve PDE properties which have been investigated in detail. The CMOS SPADs are designed in p+/n-well/deep n-well (DNW) structure with the p-sub and the p-well guard ring (GR). The simulation results show that with the p-well GR, the quantum efficiency (QE) is about 80% with the breakdown voltage of 12.7 V, the unit responsivity is as high as 0.38 A/W and the PDE of 51% and 53% is obtained when the excess bias is at 1 V and 2 V, respectively. The dark count rate (DCR) is 6.2 kHz when bias voltage is 14 V. With the p-sub GR, the breakdown voltage is 13 V, the unit responsivity is up to 0.26 A/W, the QE is 58%, the PDE is 33% and 37% at excess bias of 1 V and 2 V, respectively. The DCR is 3.4 kHz at reverse bias voltage of 14 V.

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