scholarly journals CONVERGENCE OF PARALLEL ITERATIVE ALGORITHMS FOR A SYSTEM OF NONLINEAR VARIATIONAL INEQUALITIES IN BANACH SPACES

2016 ◽  
Vol 34 (1_2) ◽  
pp. 61-73
Author(s):  
JAE UG JEONG
Keyword(s):  
Variational Inequalities ◽  
Banach Spaces ◽  
Iterative Algorithms ◽  
Parallel Iterative Algorithms ◽  
Parallel Iterative

scholarly journals Convergence of Some Iterative Algorithms for System of Generalized Set-Valued Variational Inequalities

2021 ◽  
Vol 2021 ◽  
pp. 1-15
Author(s):  
M. Akram ◽  
Aysha Khan ◽  
M. Dilshad
Keyword(s):  
Variational Inequalities ◽  
Strong Convergence ◽  
Convergence Analysis ◽  
Iterative Algorithm ◽  
Hilbert Spaces ◽  
Iterative Algorithms ◽  
Existence Of A Solution ◽  
Banach Contraction ◽  
Parallel Iterative Algorithms ◽  
Parallel Iterative

In this article, we consider and study a system of generalized set-valued variational inequalities involving relaxed cocoercive mappings in Hilbert spaces. Using the projection method and Banach contraction principle, we prove the existence of a solution for the considered problem. Further, we propose an iterative algorithm and discuss its convergence. Moreover, we establish equivalence between the system of variational inequalities and altering points problem. Some parallel iterative algorithms are proposed, and the strong convergence of the sequences generated by these iterative algorithms is discussed. Finally, a numerical example is constructed to illustrate the convergence analysis of the proposed parallel iterative algorithms.

scholarly journals Parallel Jacobi EVD Methods on Integrated Circuits

VLSI Design ◽  
2014 ◽  
Vol 2014 ◽  
pp. 1-9 ◽  
Author(s):  
Chi-Chia Sun ◽  
Jürgen Götze ◽  
Gene Eu Jan
Keyword(s):  
Integrated Circuits ◽  
Array Signal Processing ◽  
Iterative Algorithms ◽  
Computation Time ◽  
Doa Estimation ◽  
Design Criteria ◽  
Design Strategies ◽  
Signal Processing Algorithms ◽  
Parallel Iterative Algorithms ◽  
Parallel Iterative

Design strategies for parallel iterative algorithms are presented. In order to further study different tradeoff strategies in design criteria for integrated circuits, A 10 × 10 Jacobi Brent-Luk-EVD array with the simplified μ-CORDIC processor is used as an example. The experimental results show that using the μ-CORDIC processor is beneficial for the design criteria as it yields a smaller area, faster overall computation time, and less energy consumption than the regular CORDIC processor. It is worth to notice that the proposed parallel EVD method can be applied to real-time and low-power array signal processing algorithms performing beamforming or DOA estimation.

scholarly journals Convergence theorems for composite viscosity approaches to systems variational inequalities in Banach spaces

Filomat ◽  
2019 ◽  
Vol 33 (19) ◽  
pp. 6267-6281
Author(s):  
Lu-Chuan Ceng ◽  
Jen-Chih Yao ◽  
Yonghong Yao
Keyword(s):  
Variational Inequality ◽  
Variational Inequalities ◽  
Strong Convergence ◽  
Banach Spaces ◽  
Nonexpansive Mappings ◽  
Iterative Algorithms ◽  
Infinite Family ◽  
General System ◽  
Inequality Constraint ◽  
Implicit And Explicit

In this paper, we study a general system of variational inequalities with a hierarchical variational inequality constraint for an infinite family of nonexpansive mappings. We introduce general implicit and explicit iterative algorithms. We prove the strong convergence of the sequences generated by the proposed iterative algorithms to a solution of the studied problems.

scholarly journals A VLSI design concept for parallel iterative algorithms

2009 ◽  
Vol 7 ◽  
pp. 95-100 ◽  
Author(s):  
C. C. Sun ◽  
J. Götze
Keyword(s):  
Iterative Algorithm ◽  
Parallel Implementation ◽  
Vlsi Design ◽  
Iterative Algorithms ◽  
Point Of View ◽  
Design Strategies ◽  
Nano Technology ◽  
Present Design ◽  
Parallel Iterative Algorithms ◽  
Parallel Iterative

Abstract. Modern VLSI manufacturing technology has kept shrinking down to the nanoscale level with a very fast trend. Integration with the advanced nano-technology now makes it possible to realize advanced parallel iterative algorithms directly which was almost impossible 10 years ago. In this paper, we want to discuss the influences of evolving VLSI technologies for iterative algorithms and present design strategies from an algorithmic and architectural point of view. Implementing an iterative algorithm on a multiprocessor array, there is a trade-off between the performance/complexity of processors and the load/throughput of interconnects. This is due to the behavior of iterative algorithms. For example, we could simplify the parallel implementation of the iterative algorithm (i.e., processor elements of the multiprocessor array) in any way as long as the convergence is guaranteed. However, the modification of the algorithm (processors) usually increases the number of required iterations which also means that the switch activity of interconnects is increasing. As an example we show that a 25×25 full Jacobi EVD array could be realized into one single FPGA device with the simplified μ-rotation CORDIC architecture.

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