scholarly journals A decentralized convergence detection algorithm for asynchronous parallel iterative algorithms

2005 ◽  
Vol 16 (1) ◽  
pp. 4-13 ◽  
Author(s):  
J.M. Bahi ◽  
S. Contassot-Vivier ◽  
R. Couturier ◽  
F. Vernier
Keyword(s):  
Iterative Algorithms ◽  
Detection Algorithm ◽  
Parallel Iterative Algorithms ◽  
Parallel Iterative ◽  
Asynchronous Parallel

scholarly journals Parallel Jacobi EVD Methods on Integrated Circuits

VLSI Design ◽  
2014 ◽  
Vol 2014 ◽  
pp. 1-9 ◽  
Author(s):  
Chi-Chia Sun ◽  
Jürgen Götze ◽  
Gene Eu Jan
Keyword(s):  
Integrated Circuits ◽  
Array Signal Processing ◽  
Iterative Algorithms ◽  
Computation Time ◽  
Doa Estimation ◽  
Design Criteria ◽  
Design Strategies ◽  
Signal Processing Algorithms ◽  
Parallel Iterative Algorithms ◽  
Parallel Iterative

Design strategies for parallel iterative algorithms are presented. In order to further study different tradeoff strategies in design criteria for integrated circuits, A 10 × 10 Jacobi Brent-Luk-EVD array with the simplified μ-CORDIC processor is used as an example. The experimental results show that using the μ-CORDIC processor is beneficial for the design criteria as it yields a smaller area, faster overall computation time, and less energy consumption than the regular CORDIC processor. It is worth to notice that the proposed parallel EVD method can be applied to real-time and low-power array signal processing algorithms performing beamforming or DOA estimation.

scholarly journals A VLSI design concept for parallel iterative algorithms

2009 ◽  
Vol 7 ◽  
pp. 95-100 ◽  
Author(s):  
C. C. Sun ◽  
J. Götze
Keyword(s):  
Iterative Algorithm ◽  
Parallel Implementation ◽  
Vlsi Design ◽  
Iterative Algorithms ◽  
Point Of View ◽  
Design Strategies ◽  
Nano Technology ◽  
Present Design ◽  
Parallel Iterative Algorithms ◽  
Parallel Iterative

Abstract. Modern VLSI manufacturing technology has kept shrinking down to the nanoscale level with a very fast trend. Integration with the advanced nano-technology now makes it possible to realize advanced parallel iterative algorithms directly which was almost impossible 10 years ago. In this paper, we want to discuss the influences of evolving VLSI technologies for iterative algorithms and present design strategies from an algorithmic and architectural point of view. Implementing an iterative algorithm on a multiprocessor array, there is a trade-off between the performance/complexity of processors and the load/throughput of interconnects. This is due to the behavior of iterative algorithms. For example, we could simplify the parallel implementation of the iterative algorithm (i.e., processor elements of the multiprocessor array) in any way as long as the convergence is guaranteed. However, the modification of the algorithm (processors) usually increases the number of required iterations which also means that the switch activity of interconnects is increasing. As an example we show that a 25×25 full Jacobi EVD array could be realized into one single FPGA device with the simplified μ-rotation CORDIC architecture.

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