scholarly journals Fixed-Point Arithmetic in FPGA

10.14311/692 ◽  
2005 ◽  
Vol 45 (2) ◽  
Author(s):  
M. Bečvář ◽  
P. Štukjunger
Keyword(s):  
Fixed Point ◽  
Integrated Circuits ◽  
Integrated Circuit ◽  
Digital Integrated Circuits ◽  
Arithmetic Operations ◽  
Gate Arrays ◽  
Fixed Point Arithmetic ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
Point Arithmetic

Arithmetic operations are among the most frequently-used operations in contemporary digital integrated circuits. Various structures have been designed, utilizing different features of IC architectures. Nevertheless, there are very few studies that consider the design of arithmetic operations in Field Programmable Gate Arrays (FPGAs), a re-programmable type of digital integrated circuit. This text compares the results achieved when implementation of basic fixed-point arithmetic units in FPGA. 

scholarly journals FPGAs in Client Compute Hardware

2021 ◽  
Author(s):  
Michael Mattioli
Keyword(s):  
Integrated Circuits ◽  
Field Programmable Gate Arrays ◽  
Gate Arrays ◽  
Application Specific Integrated Circuits ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
And Performance ◽  
Application Specific

<div>Field-programmable gate arrays (FPGAs) are remarkably versatile. FPGAs are used in a wide variety of applications and industries where use of application-specific integrated circuits (ASICs) is less economically feasible. Despite the area, cost, and power challenges designers face when integrating FPGAs into devices, they provide significant security and performance benefits. Many of these benefits can be realized in client compute hardware such as laptops, tablets, and smartphones.</div>

Dynamically Reconfigurable Embedded Architectures for Safe Transportation Systems

2014 ◽  
pp. 347-371 ◽  
Author(s):  
Naim Harb ◽  
Smail Niar ◽  
Mazen A. R. Saghir
Keyword(s):  
Integrated Circuits ◽  
Embedded System ◽  
Transportation Systems ◽  
Base System ◽  
Dynamic Partial Reconfiguration ◽  
Dynamically Reconfigurable ◽  
Gate Arrays ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
Mtt Algorithm

Embedded system designers are increasingly relying on Field Programmable Gate Arrays (FPGAs) as target design platforms. Today's FPGAs provide high levels of logic density and rich sets of embedded hardware components. They are also inherently flexible and can be easily and quickly modified to meet changing applications or system requirements. On the other hand, FPGAs are generally slower and consume more power than Application-Specific Integrated Circuits (ASICs). However, advances in FPGA architectures, such as Dynamic Partial Reconfiguration (DPR), are helping bridge this gap. DPR enables a portion of an FPGA device to be reconfigured while the device is still operating. This chapter explores the advantage of using the DPR feature in an automotive system. The authors implement a Driver Assistant System (DAS) based on a Multiple Target Tracking (MTT) algorithm as the automotive base system. They show how the DAS architecture can be adjusted dynamically to different scenario situations to provide interesting functionalities to the driver.

scholarly journals A P4-Enabled RINA Interior Router for Software-Defined Data Centers

Computers ◽  
2020 ◽  
Vol 9 (3) ◽  
pp. 70
Author(s):  
Carolina Fernández ◽  
Sergio Giménez ◽  
Eduard Grasa ◽  
Steve Bunch
Keyword(s):  
Integrated Circuit ◽  
High Performance ◽  
Data Transfer ◽  
Great Promise ◽  
Gate Arrays ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
Application Specific Integrated Circuit ◽  
Networking Technologies ◽  
Application Specific

The lack of high-performance RINA (Recursive InterNetwork Architecture) implementations to date makes it hard to experiment with RINA as an underlay networking fabric solution for different types of networks, and to assess RINA’s benefits in practice on scenarios with high traffic loads. High-performance router implementations typically require dedicated hardware support, such as FPGAs (Field Programmable Gate Arrays) or specialized ASICs (Application Specific Integrated Circuit). With the advance of hardware programmability in recent years, new possibilities unfold to prototype novel networking technologies. In particular, the use of the P4 programming language for programmable ASICs holds great promise for developing a RINA router. This paper details the design and part of the implementation of the first P4-based RINA interior router, which reuses the layer management components of the IRATI Linux-based RINA implementation and implements the data-transfer components using a P4 program. We also describe the configuration and testing of our initial deployment scenarios, using ancillary open-source tools such as the P4 reference test software switch (BMv2) or the P4Runtime API.

scholarly journals mNet2FPGA: A Design Flow for Mapping a Fixed-Point CNN to Zynq SoC FPGA

Electronics ◽  
2020 ◽  
Vol 9 (11) ◽  
pp. 1823
Author(s):  
Tomyslav Sledevič ◽  
Artūras Serackis
Keyword(s):  
Neural Networks ◽  
Fixed Point ◽  
Processing System ◽  
Design Flow ◽  
Feature Maps ◽  
Gate Arrays ◽  
The Core ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
Fully Connected

The convolutional neural networks (CNNs) are a computation and memory demanding class of deep neural networks. The field-programmable gate arrays (FPGAs) are often used to accelerate the networks deployed in embedded platforms due to the high computational complexity of CNNs. In most cases, the CNNs are trained with existing deep learning frameworks and then mapped to FPGAs with specialized toolflows. In this paper, we propose a CNN core architecture called mNet2FPGA that places a trained CNN on a SoC FPGA. The processing system (PS) is responsible for convolution and fully connected core configuration according to the list of prescheduled instructions. The programmable logic holds cores of convolution and fully connected layers. The hardware architecture is based on the advanced extensible interface (AXI) stream processing with simultaneous bidirectional transfers between RAM and the CNN core. The core was tested on a cost-optimized Z-7020 FPGA with 16-bit fixed-point VGG networks. The kernel binarization and merging with the batch normalization layer were applied to reduce the number of DSPs in the multi-channel convolutional core. The convolutional core processes eight input feature maps at once and generates eight output channels of the same size and composition at 50 MHz. The core of the fully connected (FC) layer works at 100 MHz with up to 4096 neurons per layer. In a current version of the CNN core, the size of the convolutional kernel is fixed to 3×3. The estimated average performance is 8.6 GOPS for VGG13 and near 8.4 GOPS for VGG16/19 networks.

Field-Programmable Gate Array

2021 ◽  
pp. 257-270
Author(s):  
Mário Pereira Véstias
Keyword(s):  
Integrated Circuits ◽  
Field Programmable Gate Array ◽  
Field Programmable Gate Arrays ◽  
Software Systems ◽  
Reconfigurable Logic ◽  
Memory Cache ◽  
Gate Arrays ◽  
Field Programmable ◽  
Programmable Device ◽  
Programmable Gate Arrays

Field-programmable gate arrays (FPGAs) are integrated circuits whose logic and their interconnections are configurable. These devices are field-programmable, that is, they can be configured by the hardware designer without any intervention of the manufacturer. Most FPGAs can be reprogrammed as many times as we want with a vast variety of digital circuits. Some recent FPGA families are system-on-chips (SoC) with one or more microprocessor cores, memory, cache, and reconfigurable logic allowing the implementation of complex hardware/software systems in a single programmable device. This article focuses on the architecture of FPGAs, including the so called SoC FPGA. It explains the main blocks of the FPGA, how they have evolved along the last decades and the perspectives of next generation FPGAs. It also describes some applicability areas and how its architecture have evolved to adapt to some of these target markets.

scholarly journals FPGAs in Client Compute Hardware

2021 ◽  
Author(s):  
Michael Mattioli
Keyword(s):  
Integrated Circuits ◽  
Field Programmable Gate Arrays ◽  
Gate Arrays ◽  
Application Specific Integrated Circuits ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
And Performance ◽  
Application Specific

<div>Field-programmable gate arrays (FPGAs) are remarkably versatile. FPGAs are used in a wide variety of applications and industries where use of application-specific integrated circuits (ASICs) is less economically feasible. Despite the area, cost, and power challenges designers face when integrating FPGAs into devices, they provide significant security and performance benefits. Many of these benefits can be realized in client compute hardware such as laptops, tablets, and smartphones.</div>

scholarly journals Implementación electrónica basada en FPAA del oscilador caótico de Lorenz

2020 ◽  
pp. 14-22
Author(s):  
Alejandro SILVA-JUÁREZ ◽  
Jaime ESTEVEZ-CARREÓN ◽  
Juan Jorge PONCE-MELLADO ◽  
Gustavo HERRERA-SÁNCHEZ
Keyword(s):  
Integrated Circuit ◽  
Secure Communication ◽  
Communication Systems ◽  
Computer Arithmetic ◽  
Chaotic Oscillators ◽  
Random Number Generators ◽  
Gate Arrays ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
Chaotic Circuits

Nowadays, chaotic systems are very interesting topics for engineers, physicists and mathematicians because most real physical systems are inherently non-linear in nature. The first electronic implementations of autonomous chaotic oscillators were developed using operational amplifiers and diodes, different references detail implementations of chaotic circuits and systems using analog integrated circuit technology, discrete devices such as FPGA (Field programmable gate arrays), microcontrollers, etc. However, analog implementations suffer the problem of sensitivity of analog component values and digital implementations suffer the problem of degradation due to the reduced number of bits to perform computer arithmetic operations. The systems of differential equations that model the chaotic oscillators require integrators that can be implemented with FPAA's (Field programmable analogue array), in this work electronic implementations are developed that are measured in laboratory conditions to observe experimental chaotic attractors, which will be used in the implementation of random number generators and secure communication systems for image encryption.

Sign in / Sign up

Export Citation Format

Share Document