Silicon Photonics 8×8 Broadband Optical Switch

Author(s):  
Long Chen
Author(s):  
Hitoshi Kawashima ◽  
Keijiro Suzuki ◽  
Ken Tanizawa ◽  
Satoshi Suda ◽  
Guangwei Cong ◽  
...  

2020 ◽  
Vol 38 (2) ◽  
pp. 233-239 ◽  
Author(s):  
Keijiro Suzuki ◽  
Ryotaro Konoike ◽  
Satoshi Suda ◽  
Hiroyuki Matsuura ◽  
Shu Namiki ◽  
...  

Author(s):  
Stefano Tondini ◽  
Astghik Chalyan ◽  
Giorgio Fontana ◽  
Lorenzo Pavesi ◽  
Nikola Zečević ◽  
...  

2014 ◽  
Vol 614 ◽  
pp. 233-236
Author(s):  
Wan Jun Wang ◽  
Heng Zhao ◽  
Wei Feng Guo ◽  
Hai Feng Shao ◽  
Ting Hu ◽  
...  

We report the experimental demonstration of a 2×2 electro-optical switch in silicon-on-insulator. By controlling electro-optical phase shifter, light from any input waveguide can be directed to any output waveguide. Furthermore, the proposed optical switch can be expanded to be 1×N and N×N optical switch for optical beam forming network. The switch is fabricated by CMOS technology. In experiment, full 2×2 switching functionality is demonstrated at wavelength of 1.55 μm, with an average crosstalk of-14.6 dB and compact size of 300X100 um2.


2019 ◽  
Vol 37 (1) ◽  
pp. 131-137 ◽  
Author(s):  
Takayuki Kurosu ◽  
Takashi Inoue ◽  
Keijiro Suzuki ◽  
Satoshi Suda ◽  
Shu Namiki

Electronics ◽  
2019 ◽  
Vol 8 (8) ◽  
pp. 844 ◽  
Author(s):  
Muhammad Rehan Yahya ◽  
Ning Wu ◽  
Gaizhen Yan ◽  
Tanveer Ahmed ◽  
Jinbao Zhang ◽  
...  

Silicon photonics has become a commonly used paradigm for on-chip interconnects to meet the requirements of higher bandwidth in computationally intensive applications for manycore processors. Design of an optical switch is a vital aspect while constructing an optical NoC topology which influences the performance of network. We present a HoneyComb optimized reconfigurable optical switch (HCROS), a 6 × 6 non-blocking optical switch where optimized reconfiguration of optical links utilizing the states of basic 2 × 2 optical switching elements (OSE) was achieved while keeping the input-output (I/O) interconnection intact. The proposed 6-port HCROS architecture was further optimized to reduce the number of OSEs to minimize overall power consumption. We proposed a generic algorithm to find the optimal switching combination of OSEs for a particular I/O link to minimize the insertion loss and power consumption. In comparison to other non-blocking architectures, a maximum of 66% reduction in OSEs was observed for the optimized HCROS, which consumes only 12 OSEs. Simulations were performed for all 720 I/O links in different configurations to evaluate the power consumption and insertion loss. We observed up to 92% power savings in the case of optimized HCROS as compared to un-optimized HCROS, and a 79% minimization in insertion loss was also reported as a result of optimization.


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