scholarly journals HoneyComb ROS: A 6 × 6 Non-Blocking Optical Switch with Optimized Reconfiguration for ONoCs

Electronics ◽  
2019 ◽  
Vol 8 (8) ◽  
pp. 844 ◽  
Author(s):  
Muhammad Rehan Yahya ◽  
Ning Wu ◽  
Gaizhen Yan ◽  
Tanveer Ahmed ◽  
Jinbao Zhang ◽  
...  
Keyword(s):  
Power Consumption ◽  
Insertion Loss ◽  
Silicon Photonics ◽  
Optical Switching ◽  
Optical Switch ◽  
Input Output ◽  
Optimal Switching ◽  
Optical Links ◽  
Computationally Intensive ◽  
On Chip

Silicon photonics has become a commonly used paradigm for on-chip interconnects to meet the requirements of higher bandwidth in computationally intensive applications for manycore processors. Design of an optical switch is a vital aspect while constructing an optical NoC topology which influences the performance of network. We present a HoneyComb optimized reconfigurable optical switch (HCROS), a 6 × 6 non-blocking optical switch where optimized reconfiguration of optical links utilizing the states of basic 2 × 2 optical switching elements (OSE) was achieved while keeping the input-output (I/O) interconnection intact. The proposed 6-port HCROS architecture was further optimized to reduce the number of OSEs to minimize overall power consumption. We proposed a generic algorithm to find the optimal switching combination of OSEs for a particular I/O link to minimize the insertion loss and power consumption. In comparison to other non-blocking architectures, a maximum of 66% reduction in OSEs was observed for the optimized HCROS, which consumes only 12 OSEs. Simulations were performed for all 720 I/O links in different configurations to evaluate the power consumption and insertion loss. We observed up to 92% power savings in the case of optimized HCROS as compared to un-optimized HCROS, and a 79% minimization in insertion loss was also reported as a result of optimization.

scholarly journals Six-port optical switch for cluster-mesh photonic network-on-chip

Nanophotonics ◽  
2018 ◽  
Vol 7 (5) ◽  
pp. 827-835 ◽  
Author(s):  
Hao Jia ◽  
Ting Zhou ◽  
Yunchou Zhao ◽  
Yuhao Xia ◽  
Jincheng Dai ◽  
...  
Keyword(s):  
High Performance ◽  
Optical Switching ◽  
Optical Switch ◽  
Optical Signal ◽  
Network On Chip ◽  
Transmission Experiment ◽  
Photonic Network ◽  
Benes Network ◽  
On Chip ◽  
Spectral Responses

AbstractPhotonic network-on-chip for high-performance multi-core processors has attracted substantial interest in recent years as it offers a systematic method to meet the demand of large bandwidth, low latency and low power dissipation. In this paper we demonstrate a non-blocking six-port optical switch for cluster-mesh photonic network-on-chip. The architecture is constructed by substituting three optical switching units of typical Spanke-Benes network to optical waveguide crossings. Compared with Spanke-Benes network, the number of optical switching units is reduced by 20%, while the connectivity of routing path is maintained. By this way the footprint and power consumption can be reduced at the expense of sacrificing the network latency performance in some cases. The device is realized by 12 thermally tuned silicon Mach-Zehnder optical switching units. Its theoretical spectral responses are evaluated by establishing a numerical model. The experimental spectral responses are also characterized, which indicates that the optical signal-to-noise ratios of the optical switch are larger than 13.5 dB in the wavelength range from 1525 nm to 1565 nm. Data transmission experiment with the data rate of 32 Gbps is implemented for each optical link.

Piezoceramic Switches for Optical Fibres

2007 ◽  
Vol 352 ◽  
pp. 271-276 ◽  
Author(s):  
E. Haemmerle ◽  
M. Leung ◽  
K.A. Razak ◽  
M. Hodgson ◽  
Wei Gao
Keyword(s):  
Electrophoretic Deposition ◽  
Insertion Loss ◽  
Optical Switching ◽  
Measurement Accuracy ◽  
Optical Switch ◽  
Deposition Process ◽  
Performance Characteristics ◽  
Optical Fibres ◽  
Switching Speed ◽  
Future Work

This paper describes a new optical switching concept using the deflection of a piezoelectric tube manufactured by an electrophoretic deposition process. A prototype optical switch has been assembled and some of the performance characteristics have been measured, such as an insertion loss of 0.9dB, crosstalk of -47dB and switching speed from 5-15ms. The system for measuring deflection has been custom-designed and built with a measurement accuracy of 1μm. Future work involves the improvement of the piezoelectric tube performance characteristics and combining all switching components in one case so that the switch can be tested in a real network environment.

scholarly journals 2x4 Hybrid MZI-MMI Configuration with MMI Phase-shifters as a High-speed Optical Switch with Low Power Consumption

2019 ◽  
Author(s):  
Boris Niraula ◽  
Conrad Rizal
Keyword(s):  
Power Consumption ◽  
High Speed ◽  
Optical Switching ◽  
Phase Shifter ◽  
Optical Switch ◽  
Cmos Technology ◽  
Phase Shifters ◽  
Silicon On Insulator ◽  
Coupling Loss ◽  
Compact Size

This paper reports 2 × 4 hybrid Mach-zehnder interferometer (MZI) - multi-mode interferometers (MMI) based compact thermo-optical switch consisting of slab waveguides on silicon-on-insulator, SOI, platform. The device consists of two identical MMIs, each of 6 μm wide and 140 μm long connected with two phase shifters MMIs each with 2 μm wide and 8 μm long and linear tappers each 4 μm long, connected at both ends of the MMIs to minimize the power coupling loss. The loss for linear taper is found to be below 0.02dB. The footprint of the whole device is six 6 μm × 324 μm. This structure is based on unique multimode region shape, which leads optical switch to have less coupling loss and reduced cross-talk. The average thermo-optical switching power consumption is 1.4 mW, the excess losses are 0.8 dB, and the imbalances are 0.1 dB. Aluminum is used as a heating pad, and a trench is created around this pad to prevent from spreading of heat and reduce power loss almost by a factor of 2 to the adjacent phase shifter. Our new heating method has advantages of compact size and ease of fabrication with the current CMOS technology.

scholarly journals Design of a 2 × 4 Hybrid MMI-MZI Configuration with MMI Phase-shifters

2019 ◽  
Author(s):  
Boris B. Niraula ◽  
Conrad Rizal
Keyword(s):  
Power Consumption ◽  
Optical Switching ◽  
Optical Switch ◽  
Cmos Technology ◽  
Phase Shifters ◽  
Silicon On Insulator ◽  
Excess Loss ◽  
Power Coupling ◽  
Compact Size ◽  
Power Splitters

This paper reports design of a 2 × 4 hybrid multimode interferometer-Mach-zehnder interferometer (MMI-MZI) configuration and compact thermo-optical switch consisting of slab waveguides on the silicon-on-insulator (SOI), platform. The device consisted of two identical MMIs as power splitters and couplers that are connected with two identical MMI-based phase shifters, and linear tapers at both ends of the MMIs to minimize the power coupling loss. A thin Al pad is used as a heating element, and a trench is created around this pad to prevent heat from spreading and to minimize loss. The calculated average thermo-optical switching power consumption, excess loss, and power imbalance are 1.4 mW, 0.9 dB, and 0.1 dB, respectively. The overall footprint of the device is 6 × 304 μm2. The new heating method has advantages of compact size, ease of fabrication on SOI platform with the current CMOS technology, and offers low excess loss and power consumption as demanded by devices based on SOI technology. The device can act as two independent optical switches in one structure.

Efficient Instruction and Data Caching for High Performance Embedded Processors

1970 ◽  
pp. 9
Author(s):  
A. Ferrerón Labari ◽  
D. Suárez Gracia ◽  
V. Viñals Yúfera
Keyword(s):  
Embedded Systems ◽  
Power Consumption ◽  
Low Power ◽  
Interconnection Networks ◽  
High Performance ◽  
Critical Issue ◽  
Content Management ◽  
Structure Design ◽  
Portable Devices ◽  
On Chip

In the last years, embedded systems have evolved so that they offer capabilities we could only find before in high performance systems. Portable devices already have multiprocessors on-chip (such as PowerPC 476FP or ARM Cortex A9 MP), usually multi-threaded, and a powerful multi-level cache memory hierarchy on-chip. As most of these systems are battery-powered, the power consumption becomes a critical issue. Achieving high performance and low power consumption is a high complexity challenge where some proposals have been already made. Suarez et al. proposed a new cache hierarchy on-chip, the LP-NUCA (Low Power NUCA), which is able to reduce the access latency taking advantage of NUCA (Non-Uniform Cache Architectures) properties. The key points are decoupling the functionality, and utilizing three specialized networks on-chip. This structure has been proved to be efficient for data hierarchies, achieving a good performance and reducing the energy consumption. On the other hand, instruction caches have different requirements and characteristics than data caches, contradicting the low-power embedded systems requirements, especially in SMT (simultaneous multi-threading) environments. We want to study the benefits of utilizing small tiled caches for the instruction hierarchy, so we propose a new design, ID-LP-NUCAs. Thus, we need to re-evaluate completely our previous design in terms of structure design, interconnection networks (including topologies, flow control and routing), content management (with special interest in hardware/software content allocation policies), and structure sharing. In CMP environments (chip multiprocessors) with parallel workloads, coherence plays an important role, and must be taken into consideration.

scholarly journals Ultracompact and low-power-consumption silicon thermo-optic switch for high-speed data

Nanophotonics ◽  
2020 ◽  
Vol 10 (2) ◽  
pp. 937-945
Author(s):  
Ruihuan Zhang ◽  
Yu He ◽  
Yong Zhang ◽  
Shaohua An ◽  
Qingming Zhu ◽  
...  
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
High Performance ◽  
Pulse Amplitude ◽  
Telecommunication Networks ◽  
Low Power Consumption ◽  
Power Efficient ◽  
High Speed Data ◽  
On Chip

AbstractUltracompact and low-power-consumption optical switches are desired for high-performance telecommunication networks and data centers. Here, we demonstrate an on-chip power-efficient 2 × 2 thermo-optic switch unit by using a suspended photonic crystal nanobeam structure. A submilliwatt switching power of 0.15 mW is obtained with a tuning efficiency of 7.71 nm/mW in a compact footprint of 60 μm × 16 μm. The bandwidth of the switch is properly designed for a four-level pulse amplitude modulation signal with a 124 Gb/s raw data rate. To the best of our knowledge, the proposed switch is the most power-efficient resonator-based thermo-optic switch unit with the highest tuning efficiency and data ever reported.

scholarly journals Graphene Nanoribbon Gap Waveguides for Dispersionless and Low-Loss Propagation with Deep-Subwavelength Confinement

Nanomaterials ◽  
2021 ◽  
Vol 11 (5) ◽  
pp. 1302
Author(s):  
Zhiyong Wu ◽  
Lei Zhang ◽  
Tingyin Ning ◽  
Hong Su ◽  
Irene Ling Li ◽  
...  
Keyword(s):  
High Performance ◽  
Chemical Potential ◽  
Shape Change ◽  
Optical Switch ◽  
Pulse Amplitude ◽  
Propagation Distance ◽  
Graphene Nanoribbon ◽  
Low Loss ◽  
High Loss ◽  
On Chip

Surface plasmon polaritons (SPPs) have been attracting considerable attention owing to their unique capabilities of manipulating light. However, the intractable dispersion and high loss are two major obstacles for attaining high-performance plasmonic devices. Here, a graphene nanoribbon gap waveguide (GNRGW) is proposed for guiding dispersionless gap SPPs (GSPPs) with deep-subwavelength confinement and low loss. An analytical model is developed to analyze the GSPPs, in which a reflection phase shift is employed to successfully deal with the influence caused by the boundaries of the graphene nanoribbon (GNR). It is demonstrated that a pulse with a 4 μm bandwidth and a 10 nm mode width can propagate in the linear passive system without waveform distortion, which is very robust against the shape change of the GNR. The decrease in the pulse amplitude is only 10% for a propagation distance of 1 μm. Furthermore, an array consisting of several GNRGWs is employed as a multichannel optical switch. When the separation is larger than 40 nm, each channel can be controlled independently by tuning the chemical potential of the corresponding GNR. The proposed GNRGW may raise great interest in studying dispersionless and low-loss nanophotonic devices, with potential applications in the distortionless transmission of nanoscale signals, electro-optic nanocircuits, and high-density on-chip communications.

scholarly journals Exploring a New Adaptive Routing Based on the Dijkstra Algorithm in Optical Networks-on-Chip

Micromachines ◽  
2021 ◽  
Vol 12 (1) ◽  
pp. 54
Author(s):  
Yan-Li Zheng ◽  
Ting-Ting Song ◽  
Jun-Xiong Chai ◽  
Xiao-Ping Yang ◽  
Meng-Meng Yu ◽  
...  
Keyword(s):  
Power Consumption ◽  
Power Control ◽  
Optical Networks ◽  
Output Power ◽  
Network Performance ◽  
Transmission Loss ◽  
Adaptive Routing ◽  
Dijkstra Algorithm ◽  
Networks On Chip ◽  
On Chip

The photoelectric hybrid network has been proposed to achieve the ultrahigh bandwidth, lower delay, and less power consumption for chip multiprocessor (CMP) systems. However, a large number of optical elements used in optical networks-on-chip (ONoCs) generate high transmission loss which will influence network performance severely and increase power consumption. In this paper, the Dijkstra algorithm is adopted to realize adaptive routing with minimum transmission loss of link and reduce the output power of the link transmitter in mesh-based ONoCs. The numerical simulation results demonstrate that the transmission loss of a link in optimized power control based on the Dijkstra algorithm could be maximally reduced compared with traditional power control based on the dimensional routing algorithm. Additionally, it has a greater advantage in saving the average output power of optical transmitter compared to the adaptive power control in previous studies, while the network size expands. With the aid of simulation software OPNET, the network performance simulations in an optimized network revealed that the end-to-end (ETE) latency and throughput are not vastly reduced in regard to a traditional network. Hence, the optimized power control proposed in this paper can greatly reduce the power consumption of s network without having a big impact on network performance.

scholarly journals 1.0 V-0.18 µm CMOS Tunable Low Pass Filters with 73 dB DR for On-Chip Sensing Acquisition Systems

Electronics ◽  
2021 ◽  
Vol 10 (5) ◽  
pp. 563
Author(s):  
Jorge Pérez-Bailón ◽  
Belén Calvo ◽  
Nicolás Medrano
Keyword(s):  
Power Consumption ◽  
Dynamic Range ◽  
Low Voltage ◽  
Cutoff Frequency ◽  
Cmos Technology ◽  
Active Area ◽  
Current Steering ◽  
Low Pass ◽  
On Chip ◽  
Low Pass Filters

This paper presents a new approach based on the use of a Current Steering (CS) technique for the design of fully integrated Gm–C Low Pass Filters (LPF) with sub-Hz to kHz tunable cut-off frequencies and an enhanced power-area-dynamic range trade-off. The proposed approach has been experimentally validated by two different first-order single-ended LPFs designed in a 0.18 µm CMOS technology powered by a 1.0 V single supply: a folded-OTA based LPF and a mirrored-OTA based LPF. The first one exhibits a constant power consumption of 180 nW at 100 nA bias current with an active area of 0.00135 mm2 and a tunable cutoff frequency that spans over 4 orders of magnitude (~100 mHz–152 Hz @ CL = 50 pF) preserving dynamic figures greater than 78 dB. The second one exhibits a power consumption of 1.75 µW at 500 nA with an active area of 0.0137 mm2 and a tunable cutoff frequency that spans over 5 orders of magnitude (~80 mHz–~1.2 kHz @ CL = 50 pF) preserving a dynamic range greater than 73 dB. Compared with previously reported filters, this proposal is a competitive solution while satisfying the low-voltage low-power on-chip constraints, becoming a preferable choice for general-purpose reconfigurable front-end sensor interfaces.

scholarly journals Spectroscopy-on-chip applications of silicon photonics

2013 ◽  
Author(s):  
Roel Baets ◽  
Ananth Z. Subramanian ◽  
Ashim Dhakal ◽  
Shankar K. Selvaraja ◽  
Katarzyna Komorowska ◽  
...  
Keyword(s):  
Silicon Photonics ◽  
On Chip
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