Photon Counting Chirped AM Ladar: Concept and Simulation Results

Bitstream Photon Counting Chirped AM Lidar with a Dual Unipolar Signal

10.31224/osf.io/smrac ◽

2020 ◽

Author(s):

Brian Redman

Keyword(s):

Integrated Circuits ◽

Phase I ◽

Signal To Noise Ratio ◽

Photon Counting ◽

Complementary Metal Oxide Semiconductor ◽

Local Oscillator ◽

Sinusoidal Signal ◽

Oxide Semiconductor ◽

Quadrature Phase ◽

Simulation Results

This paper is a follow-up to three previous papers: the first introducing the new Bitstream Photon Counting Chirped Amplitude Modulation (AM) Lidar (PC-CAML) with the unipolar Digital Logic Local Oscillator (DLLO) concept, the second introducing the improvement thereof using the bipolar DLLO, and the third introducing the improvement of digital In-phase and Quadrature-phase (I/Q) demodulation.In that previous work, the signal was a single unipolar chirped sinusoidal or square wave. This paper introduces a new bitstream PC-CAML transceiver architecture that combines two unipolar chirped signals, referred to as the dual unipolar signal, to form a single bipolar signal in the receiver. (patent pending) This bipolar signal is mixed with the bipolar DLLOs in the in-phase (I) digital mixing and quadrature-phase (Q) digital mixing channels for digital I/Q demodulation for improved signal-to-noise ratio (SNR) compared to that when using a single unipolar signal.The simulation results presented in this paper indicate an SNR improvement for the dual unipolar chirped sinusoidal signal bitstream PC-CAML compared to that of the unipolar chirped sinusoidal signal bitstream PC-CAML (both with bipolar DLLOs and digital I/Q demodulation) of from about 3 dB to about 6 dB for signals below the onset of receiver saturation, and an improvement for maximum achievable SNR of about 13 dB if the receiver is allowed to saturate.The bitstream PC-CAML with a dual unipolar signal and bipolar DLLOs with digital I/Q demodulation architecture discussed in this paper adds complexity to the transmitter and receiver compared to the architectures presented in the previous papers. Whether or not this additional complexity is worth the improved SNR will have to be decided as part of system trade studies for particular systems and their applications.However, the new architecture still retains the key advantages of the previous bitstream PC-CAML architectures since it still replaces bulky, power-hungry, and expensive wideband RF analog electronics in the receiver with digital components that can be implemented in inexpensive silicon complementary metal-oxide-semiconductor (CMOS) read-out integrated circuits (ROICs) to make the bitstream PC-CAML with a DLLO more suitable for compact lidar-on-a-chip systems and lidar array receivers than previous standard PC-CAML systems.This paper introduces the dual unipolar signal and bipolar DLLOs with digital I/Q demodulation transceiver architecture for bitstream PC-CAML, and presents the initial SNR theory with comparisons to Monte Carlo simulation results.

Download Full-text

Bipolar Digital Logic Local Oscillator for Bitstream Photon Counting Chirped AM Lidar

10.31224/osf.io/7mcbg ◽

2019 ◽

Author(s):

Brian Redman

Keyword(s):

Monte Carlo Simulation ◽

Monte Carlo ◽

Signal To Noise Ratio ◽

Photon Counting ◽

Local Oscillator ◽

Digital Logic ◽

Quantization Noise ◽

Signal To Noise ◽

Simulation Results ◽

Noise Ratio

This paper is a follow-up to a previous paper introducing the new bitstream Photon Counting Chirped Amplitude Modulation (AM) Lidar (PC-CAML) with a Digital Logic Local Oscillator (DLLO) concept. In that previous work, the DLLO was unipolar. In this paper, a new bipolar DLLO for the bitstream PC-CAML is introduced (patent pending). The bipolar DLLO retains the key advantages of the unipolar DLLO for the bitstream PC-CAML since it also replaces bulky, power-hungry, and expensive wideband RF analog electronics with digital components that can be implemented in inexpensive silicon complementary metal-oxide-semiconductor (CMOS) read-out integrated circuits (ROICs) to make the bitstream PC-CAML with a DLLO more suitable for compact lidar-on-a-chip systems and lidar array receivers than previous PC-CAML systems. In addition, the bipolar DLLO improves the electrical power signal-to-noise ratio (SNR) of the bitstream PC-CAML by about 2.5 dB compared to that of the unipolar DLLO as shown by the theoretical and Monte Carlo simulation results presented in this paper. Theoretically, there should be a 3 dB improvement for the bipolar DLLO from the elimination of the signal power loss to the DC component of the intermediate frequency (IF) spectrum that occurs with the unipolar DLLO. However, this improvement is partially offset by a higher quantization noise for the bipolar DLLO compared to that of the unipolar DLLO as explained in this paper.This paper introduces the bipolar DLLO for bitstream PC-CAML concept and presents the initial signal-to-noise ratio (SNR) theory with comparisons to Monte Carlo simulation results.

Download Full-text

Time Correlated Single Photon Counting System for Optical Measurements

International Journal of Electronics and Telecommunications ◽

10.2478/v10177-010-0040-1 ◽

2010 ◽

Vol 56 (3) ◽

pp. 301-306

Author(s):

Artur Trybuła ◽

Grzegorz Domański ◽

Bogumił Konarzewski ◽

Janusz Marzec ◽

Krzysztof Zaremba ◽

...

Keyword(s):

Single Photon ◽

Photon Counting ◽

High Sensitivity ◽

Optical Measurements ◽

Counting System ◽

Single Photon Counting ◽

Simulation Results ◽

Biomedical Measurements ◽

Mean Time ◽

Good Agreement

Time Correlated Single Photon Counting System for Optical MeasurementsThe high sensitivity time correlated single photon counting system (with photomultiplier tube) for biomedical measurements was designed and tested. Photon time of flight through a parafine wax phantom was modeled by Monte Carlo simulation and next measured by the device. Mean time delay introduced by a phantom is in a good agreement with simulation results. The results presented in this paper demonstrate the feasibility of measuring the optical response with the device.

Download Full-text

Simulation results for PLATO: a prototype hybrid X-ray photon counting detector with a low energy threshold for fusion plasma diagnostics

Journal of Instrumentation ◽

10.1088/1748-0221/12/01/c01036 ◽

2017 ◽

Vol 12 (01) ◽

pp. C01036-C01036

Author(s):

A. Habib ◽

M. Menouni ◽

P. Pangaud ◽

C. Fenzi ◽

G. Colledani ◽

...

Keyword(s):

Plasma Diagnostics ◽

Photon Counting ◽

Low Energy ◽

Energy Threshold ◽

Fusion Plasma ◽

X Ray ◽

Photon Counting Detector ◽

Simulation Results

Download Full-text

Vernier time-to-digital converter with ring oscillators for in-pixel time-of-arrival and time-over-threshold measurement in 28 nm CMOS

Journal of Instrumentation ◽

10.1088/1748-0221/16/12/c12010 ◽

2021 ◽

Vol 16 (12) ◽

pp. C12010

Author(s):

L.A. Kadlubowski ◽

P. Kmon

Keyword(s):

Single Photon ◽

Photon Counting ◽

Cmos Technology ◽

Time Of Arrival ◽

Ring Oscillators ◽

Digital Converter ◽

Time To Digital Converter ◽

Recording Channel ◽

Simulation Results ◽

28 Nm

Abstract The paper describes a design of a prototype chip in 28 nm CMOS technology, consisting of 8 × 4 pixels with 50 μm pitch, dedicated for the precise measurement of Time-of-Arrival (ToA) and Time-over-Threshold (ToT) with a resolution within the picosecond range. To address this requirement, in-pixel Vernier time-to-digital converter (TDC) has been implemented, which utilizes two ring oscillators per pixel. Overall chip architecture is introduced as well as pixel architecture and selected simulation results. The pixel consists of a recording channel and TDC part. The recording channel is composed of an inverter-based front-end amplifier with Zimmerman feedback, a discriminator, a calibration block and a threshold setting block. TDC part includes two ring oscillators together with their calibration blocks and additional logic with counters/shift registers that allow for precise ToA measurement (using Vernier method) as well as ToT measurement (using one of the oscillators). Alternatively, single photon counting (SPC) mode can be used. Frequency of oscillators is set in three steps. First, two global 8-bit digital-to-analog converters (DACs) are used for initial setting of all ring oscillators. Then, per-oscillator capacitance bank and 6-bit DAC are used for fine setting. Simulation results of core blocks suggest that the ToA resolution on the order of tens of picoseconds may be achieved. The chips are already fabricated and are currently being prepared for measurements.

Download Full-text